^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * the "Intel 460GTX Chipset Software Developer's Manual":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.intel.com/design/archives/itanium/downloads/248704.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INTEL_I460_BAPBASE 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INTEL_I460_GXBCTL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define INTEL_I460_AGPSIZ 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTEL_I460_ATTBASE 0xfe200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTEL_I460_GATT_VALID (1UL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define INTEL_I460_GATT_COHERENT (1UL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The i460 can operate with large (4MB) pages, but there is no sane way to support this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * within the current kernel/DRM environment, so we disable the relevant code for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * See also comments in ia64_alloc_page()...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I460_LARGE_IO_PAGES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #if I460_LARGE_IO_PAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define I460_IO_PAGE_SHIFT i460.io_page_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define I460_IO_PAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I460_IOPAGES_PER_KPAGE (PAGE_SIZE >> I460_IO_PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I460_KPAGES_PER_IOPAGE (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I460_SRAM_IO_DISABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I460_BAPBASE_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I460_AGPSIZ_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I460_4M_PS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Control bits for Out-Of-GART coherency and Burst Write Combining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I460_GXBCTL_OOG (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I460_GXBCTL_BWC (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * gatt_table and gatt_table_real pointers a "void *"...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RD_GATT(index) readl((u32 *) i460.gatt + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The 460 spec says we have to read the last location written to make sure that all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * writes have taken effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WR_FLUSH_GATT(index) RD_GATT(index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma_addr_t addr, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void *gatt; /* ioremap'd GATT area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 io_page_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* BIOS configures chipset to one of 2 possible apbase values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 dynamic_apbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* structure for tracking partial use of 4MB GART pages: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct lp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long *alloced_map; /* bitmap of kernel-pages in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int refcount; /* number of kernel pages using the large page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 paddr; /* physical address of large page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct page *page; /* page pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } *lp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } i460;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct aper_size_info_8 i460_sizes[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * The 32GB aperture is only available with a 4M GART page size. Due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * dynamic GART page size, we can't figure out page_order or num_entries until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {32768, 0, 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {1024, 0, 0, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {256, 0, 0, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct gatt_mask i460_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .type = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int i460_fetch_size (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct aper_size_info_8 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Determine the GART page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) printk(KERN_ERR PFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "I/O (GART) page-size %luKB doesn't match expected "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "size %luKB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1UL << (i460.io_page_shift - 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 1UL << (I460_IO_PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Exit now if the IO drivers for the GART SRAMS are turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (temp & I460_SRAM_IO_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) printk(KERN_ERR PFX "AGPGART operation not possible\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Make sure we don't try to create an 2 ^ 23 entry GATT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Determine the proper APBASE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (temp & I460_BAPBASE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) i460.dynamic_apbase = INTEL_I460_BAPBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) i460.dynamic_apbase = AGP_APBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Dynamically calculate the proper num_entries and page_order values for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * the define aperture sizes. Take care not to shift off the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * values[i].size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) values[i].page_order = ilog2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Neglect control bits when matching up size_value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* There isn't anything to do here since 460 has no GART TLB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void i460_tlb_flush (struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * This utility function is needed to prevent corruption of the control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * which are stored along with the aperture size in 460's AGPSIZ register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void i460_write_agpsiz (u8 size_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ((temp & ~I460_AGPSIZ_MASK) | size_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void i460_cleanup (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct aper_size_info_8 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) previous_size = A_SIZE_8(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) i460_write_agpsiz(previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) kfree(i460.lp_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int i460_configure (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 small[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 large;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct aper_size_info_8 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) temp.large = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) current_size = A_SIZE_8(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) i460_write_agpsiz(current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Do the necessary rigmarole to read all eight bytes of APBASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * This has to be done since the AGP aperture can be above 4GB on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 460 based systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Clear BAR control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Initialize partial allocation trackers if a GART page is bigger than a kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) size = current_size->num_entries * sizeof(i460.lp_desc[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) i460.lp_desc = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!i460.lp_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int i460_create_gatt_table (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int page_order, num_entries, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Load up the fixed address of the GART SRAMS which hold our GATT table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) page_order = A_SIZE_8(temp)->page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) num_entries = A_SIZE_8(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!i460.gatt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) printk(KERN_ERR PFX "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* These are no good, the should be removed from the agp_bridge strucure... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) agp_bridge->gatt_table_real = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) agp_bridge->gatt_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) agp_bridge->gatt_bus_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < num_entries; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) WR_GATT(i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) WR_FLUSH_GATT(i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int i460_free_gatt_table (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int num_entries, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) num_entries = A_SIZE_8(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (i = 0; i < num_entries; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) WR_GATT(i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) WR_FLUSH_GATT(num_entries - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iounmap(i460.gatt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * The following functions are called when the I/O (GART) page size is smaller than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int i460_insert_memory_small_io_page (struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long paddr, io_pg_start, io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int i, j, k, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mem, pg_start, type, page_to_phys(mem->pages[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) num_entries = A_SIZE_8(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) j = io_pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) j, RD_GATT(j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) io_page_size = 1UL << I460_IO_PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) paddr = page_to_phys(mem->pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) WR_GATT(j, i460_mask_memory(agp_bridge, paddr, mem->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) WR_FLUSH_GATT(j - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int i460_remove_memory_small_io_page(struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mem, pg_start, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WR_GATT(i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) WR_FLUSH_GATT(i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #if I460_LARGE_IO_PAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * This situation is interesting since AGP memory allocations that are smaller than a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * single GART page are possible. The i460.lp_desc array tracks partial allocation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * large GART pages to work around this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * pg_num. i460.lp_desc[pg_num].paddr is the physical address of the large page and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int i460_alloc_large_page (struct lp_desc *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) size_t map_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) lp->page = alloc_pages(GFP_KERNEL, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!lp->page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) lp->alloced_map = kzalloc(map_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!lp->alloced_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __free_pages(lp->page, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) lp->paddr = page_to_phys(lp->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) lp->refcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void i460_free_large_page (struct lp_desc *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) kfree(lp->alloced_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lp->alloced_map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __free_pages(lp->page, I460_IO_PAGE_SHIFT - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int i460_insert_memory_large_io_page (struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int i, start_offset, end_offset, idx, pg, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct lp_desc *start, *end, *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) num_entries = A_SIZE_8(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Figure out what pg_start means in terms of our large GART pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (end > i460.lp_desc + num_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Check if the requested region of the aperture is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (lp = start; lp <= end; ++lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!lp->alloced_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) continue; /* OK, the entire large page is available... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for (idx = ((lp == start) ? start_offset : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (test_bit(idx, lp->alloced_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (lp = start, i = 0; lp <= end; ++lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!lp->alloced_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Allocate new GART pages... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (i460_alloc_large_page(lp) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pg = lp - i460.lp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) WR_GATT(pg, i460_mask_memory(agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lp->paddr, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) WR_FLUSH_GATT(pg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (idx = ((lp == start) ? start_offset : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) idx++, i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mem->pages[i] = lp->page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __set_bit(idx, lp->alloced_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ++lp->refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int i460_remove_memory_large_io_page (struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i, pg, start_offset, end_offset, idx, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct lp_desc *start, *end, *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) temp = agp_bridge->current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) num_entries = A_SIZE_8(temp)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Figure out what pg_start means in terms of our large GART pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (i = 0, lp = start; lp <= end; ++lp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) for (idx = ((lp == start) ? start_offset : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) idx++, i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mem->pages[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) __clear_bit(idx, lp->alloced_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) --lp->refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Free GART pages if they are unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (lp->refcount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pg = lp - i460.lp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) WR_GATT(pg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) WR_FLUSH_GATT(pg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) i460_free_large_page(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Wrapper routines to call the approriate {small_io_page,large_io_page} function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int i460_insert_memory (struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return i460_insert_memory_small_io_page(mem, pg_start, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return i460_insert_memory_large_io_page(mem, pg_start, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int i460_remove_memory (struct agp_memory *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return i460_remove_memory_small_io_page(mem, pg_start, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return i460_remove_memory_large_io_page(mem, pg_start, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * If the I/O (GART) page size is bigger than the kernel page size, we don't want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * allocate memory until we know where it is to be bound in the aperture (a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * multi-kernel-page alloc might fit inside of an already allocated GART page).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Let's just hope nobody counts on the allocated AGP memory being there before bind time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * (I don't think current drivers do)...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct page *i460_alloc_page (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) page = agp_generic_alloc_page(agp_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Returning NULL would cause problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* AK: really dubious code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) page = (void *)~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void i460_destroy_page (struct page *page, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) agp_generic_destroy_page(page, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #endif /* I460_LARGE_IO_PAGES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dma_addr_t addr, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Make sure the returned address is a valid GATT entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return bridge->driver->masks[0].mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) const struct agp_bridge_driver intel_i460_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .aperture_sizes = i460_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .size_type = U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .num_aperture_sizes = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .configure = i460_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .fetch_size = i460_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cleanup = i460_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .tlb_flush = i460_tlb_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .mask_memory = i460_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .masks = i460_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .create_gatt_table = i460_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .free_gatt_table = i460_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #if I460_LARGE_IO_PAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .insert_memory = i460_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .remove_memory = i460_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .agp_alloc_page = i460_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .agp_destroy_page = i460_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .insert_memory = i460_insert_memory_small_io_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .remove_memory = i460_remove_memory_small_io_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .cant_use_aperture = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int agp_intel_i460_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bridge->driver = &intel_i460_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) printk(KERN_INFO PFX "Detected Intel 460GX chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static void agp_intel_i460_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct pci_device_id agp_intel_i460_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .vendor = PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .device = PCI_DEVICE_ID_INTEL_84460GX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct pci_driver agp_intel_i460_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "agpgart-intel-i460",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .id_table = agp_intel_i460_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .probe = agp_intel_i460_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .remove = agp_intel_i460_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int __init agp_intel_i460_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return pci_register_driver(&agp_intel_i460_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void __exit agp_intel_i460_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pci_unregister_driver(&agp_intel_i460_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) module_init(agp_intel_i460_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) module_exit(agp_intel_i460_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MODULE_LICENSE("GPL and additional rights");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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