^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HP zx1 AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Bjorn Helgaas <bjorn.helgaas@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/acpi-ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* HP ZX1 IOC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HP_ZX1_IBASE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HP_ZX1_IMASK 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HP_ZX1_PCOM 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HP_ZX1_TCNFG 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HP_ZX1_PDIR_BASE 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HP_ZX1_IOVA_BASE GB(1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HP_ZX1_IOVA_SIZE GB(1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AGP8X_MODE_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AGP8X_MODE (1 << AGP8X_MODE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* AGP bridge need not be PCI device, but DRM thinks it is. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct pci_dev fake_bridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int hp_zx1_gart_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct aper_size_info_fixed hp_zx1_sizes[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct gatt_mask hp_zx1_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct _hp_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) volatile u8 __iomem *ioc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) volatile u8 __iomem *lba_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int lba_cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 *io_pdir; // PDIR for entire IOVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u64 *gatt; // PDIR just for GART (subset of above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 gatt_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u64 iova_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u64 gart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 gart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u64 io_pdir_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int io_pdir_owner; // do we own it, or share it with sba_iommu?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int io_tlb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int io_tlb_ps; // IOC ps config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int io_pages_per_kpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int __init hp_zx1_ioc_shared(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * IOC already configured by sba_iommu module; just use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * its setup. We assume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * - IOVA space is 1Gb in size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * - first 512Mb is IOMMU, second 512Mb is GART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (hp->io_tlb_ps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 0: hp->io_tlb_shift = 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 1: hp->io_tlb_shift = 13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 2: hp->io_tlb_shift = 14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 3: hp->io_tlb_shift = 16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) printk(KERN_ERR PFX "Invalid IOTLB page size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "configuration 0x%x\n", hp->io_tlb_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) hp->gatt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) hp->gatt_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) hp->io_page_size = 1 << hp->io_tlb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) hp->gart_size = HP_ZX1_GART_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hp->gatt_entries = hp->gart_size / hp->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Normal case when no AGP device in system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hp->gatt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) hp->gatt_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "GART disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hp_zx1_ioc_owner (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Select an IOV page size no larger than system page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (PAGE_SIZE >= KB(64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) hp->io_tlb_shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hp->io_tlb_ps = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else if (PAGE_SIZE >= KB(16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) hp->io_tlb_shift = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hp->io_tlb_ps = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } else if (PAGE_SIZE >= KB(8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) hp->io_tlb_shift = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hp->io_tlb_ps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hp->io_tlb_shift = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hp->io_tlb_ps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hp->io_page_size = 1 << hp->io_tlb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) hp->iova_base = HP_ZX1_IOVA_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) hp->gart_size = HP_ZX1_GART_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hp->gatt_entries = hp->gart_size / hp->io_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) hp_zx1_ioc_init (u64 hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hp->ioc_regs = ioremap(hpa, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!hp->ioc_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * If the IOTLB is currently disabled, we can take it over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Otherwise, we have to share with sba_iommu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (hp->io_pdir_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return hp_zx1_ioc_owner();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return hp_zx1_ioc_shared();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 pos, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ttl = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) status = readw(hpa+PCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(status & PCI_STATUS_CAP_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pos = readb(hpa+PCI_CAPABILITY_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) while (ttl-- && pos >= 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pos &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) id = readb(hpa+pos+PCI_CAP_LIST_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (id == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (id == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) hp_zx1_lba_init (u64 hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hp->lba_regs = ioremap(hpa, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!hp->lba_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (cap != PCI_CAP_ID_AGP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cap, hp->lba_cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) iounmap(hp->lba_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hp_zx1_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) size = hp_private.gart_size / MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hp_zx1_sizes[0].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hp_zx1_configure (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) agp_bridge->gart_bus_addr = hp->gart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) agp_bridge->capndx = hp->lba_cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (hp->io_pdir_owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(virt_to_phys(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) readl(hp->ioc_regs+HP_ZX1_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) readl(hp->ioc_regs+HP_ZX1_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) readl(hp->ioc_regs+HP_ZX1_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(hp->iova_base|ilog2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) readl(hp->ioc_regs+HP_ZX1_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) hp_zx1_cleanup (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (hp->ioc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (hp->io_pdir_owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) readq(hp->ioc_regs+HP_ZX1_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) iounmap(hp->ioc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (hp->lba_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) iounmap(hp->lba_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hp_zx1_tlbflush (struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writeq(hp->gart_base | ilog2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) readq(hp->ioc_regs+HP_ZX1_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (hp->io_pdir_owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) get_order(hp->io_pdir_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!hp->io_pdir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) printk(KERN_ERR PFX "Couldn't allocate contiguous "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "memory for I/O PDIR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hp->gatt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hp->gatt_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) memset(hp->io_pdir, 0, hp->io_pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < hp->gatt_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (hp->io_pdir_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) free_pages((unsigned long) hp->io_pdir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) get_order(hp->io_pdir_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) off_t j, io_pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int io_pg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) io_pg_start = hp->io_pages_per_kpage * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) io_pg_count = hp->io_pages_per_kpage * mem->page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) j = io_pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) while (j < (io_pg_start + io_pg_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (hp->gatt[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) paddr = page_to_phys(mem->pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) k < hp->io_pages_per_kpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) k++, j++, paddr += hp->io_page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hp->gatt[j] = HP_ZX1_PDIR_VALID_BIT | paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int i, io_pg_start, io_pg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) io_pg_start = hp->io_pages_per_kpage * pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) io_pg_count = hp->io_pages_per_kpage * mem->page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hp->gatt[i] = agp_bridge->scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hp_zx1_mask_memory (struct agp_bridge_data *bridge, dma_addr_t addr, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return HP_ZX1_PDIR_VALID_BIT | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct _hp_private *hp = &hp_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) command = agp_collect_device_status(bridge, mode, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) command |= 0x00000100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) agp_device_command(command, (mode & AGP8X_MODE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const struct agp_bridge_driver hp_zx1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .size_type = FIXED_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .configure = hp_zx1_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .fetch_size = hp_zx1_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .cleanup = hp_zx1_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .tlb_flush = hp_zx1_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .mask_memory = hp_zx1_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .masks = hp_zx1_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .agp_enable = hp_zx1_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .create_gatt_table = hp_zx1_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .free_gatt_table = hp_zx1_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .insert_memory = hp_zx1_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .remove_memory = hp_zx1_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .cant_use_aperture = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) error = hp_zx1_ioc_init(ioc_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) error = hp_zx1_lba_init(lba_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bridge->driver = &hp_zx1_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bridge->dev = &fake_bridge_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) error = agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hp_zx1_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static acpi_status __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) acpi_handle handle, parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct acpi_device_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u64 lba_hpa, sba_hpa, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) status = hp_acpi_csr_space(obj, &lba_hpa, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return AE_OK; /* keep looking for another bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Look for an enclosing IOC scope and find its CSR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) handle = obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) status = acpi_get_object_info(handle, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ACPI_SUCCESS(status) && (info->valid & ACPI_VALID_HID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* TBD check _CID also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) match = (strcmp(info->hardware_id.string, "HWP0001") == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) status = hp_acpi_csr_space(handle, &sba_hpa, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ACPI_SUCCESS(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) printk(KERN_ERR PFX "Detected HP ZX1 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "AGP LBA but no IOC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) status = acpi_get_parent(handle, &parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) handle = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } while (ACPI_SUCCESS(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return AE_OK; /* found no enclosing IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "(ioc=%llx, lba=%llx)\n", (char *)context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hp_zx1_gart_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) agp_hp_init (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (hp_zx1_gart_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (hp_zx1_gart_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) agp_hp_cleanup (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) module_init(agp_hp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) module_exit(agp_hp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_LICENSE("GPL and additional rights");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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