Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Transmeta's Efficeon AGPGART driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Based upon a diff by Linus around November '02.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Ported to the 2.6 kernel by Carlos Puchol <cpglinux@puchol.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * and H. Peter Anvin <hpa@transmeta.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * NOTE-cpg-040217:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   - when compiled as a module, after loading the module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *     it will refuse to unload, indicating it is in use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *     when it is not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *   - no s3 (suspend to ram) testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   - tested on the efficeon integrated nothbridge for tens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *     of iterations of starting x and glxgears.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *   - tested with radeon 9000 and radeon mobility m9 cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *   - tested with c3/c4 enabled (with the mobility m9 card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/page-flags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "intel-agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * The real differences to the generic AGP code is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * in the GART mappings - a two-level setup with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * first level being an on-chip 64-entry table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * The page array is filled through the ATTPAGE register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * (Aperture Translation Table Page Register) at 0xB8. Bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *  31:20: physical page address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *   11:9: Page Attribute Table Index (PATI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *	   must match the PAT index for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *	   mapped pages (the 2nd level page table pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *	   themselves should be just regular WB-cacheable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *	   so this is normally zero.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *      8: Present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *    7:6: reserved, write as zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *    5:0: GATT directory index: which 1st-level entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * The Efficeon AGP spec requires pages to be WB-cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * but to be explicitly CLFLUSH'd after any changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define EFFICEON_ATTPAGE	0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EFFICEON_L1_SIZE	64	/* Number of PDE pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EFFICEON_PATI		(0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EFFICEON_PRESENT	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct _efficeon_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned long l1_table[EFFICEON_L1_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) } efficeon_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct gatt_mask efficeon_generic_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{.mask = 0x00000001, .type = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* This function does the same thing as mask_memory() for this chipset... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static inline unsigned long efficeon_mask_memory(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned long addr = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return addr | 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const struct aper_size_info_lvl2 efficeon_generic_sizes[4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{256, 65536, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{128, 32768, 32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{64, 16384, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{32, 8192, 56}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * Control interfaces are largely identical to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * the legacy Intel 440BX..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int efficeon_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct aper_size_info_lvl2 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			    agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void efficeon_tlbflush(struct agp_memory * mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	printk(KERN_DEBUG PFX "efficeon_tlbflush()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void efficeon_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct aper_size_info_lvl2 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	printk(KERN_DEBUG PFX "efficeon_cleanup()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			      previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int efficeon_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u16 temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct aper_size_info_lvl2 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	printk(KERN_DEBUG PFX "efficeon_configure()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	current_size = A_SIZE_LVL2(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* aperture size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			      current_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 						    AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* agpctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* paccfg/nbxcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			      (temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* clear any possible error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int efficeon_free_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int index, freed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	for (index = 0; index < EFFICEON_L1_SIZE; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		unsigned long page = efficeon_private.l1_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			efficeon_private.l1_table[index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			free_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			freed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			agp_bridge->dev, EFFICEON_ATTPAGE, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		pci_write_config_dword(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			EFFICEON_ATTPAGE, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * Since we don't need contiguous memory we just try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * to get the gatt table once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #undef  GET_GATT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GET_GATT(addr) (efficeon_private.gatt_pages[\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	GET_PAGE_DIR_IDX(addr)]->remapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int efficeon_create_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	const int pati    = EFFICEON_PATI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	const int present = EFFICEON_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int num_entries, l1_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* There are 2^10 PTE pages per PDE page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	BUG_ON(num_entries & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	l1_pages = num_entries >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	for (index = 0 ; index < l1_pages ; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		unsigned long page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		page = efficeon_private.l1_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		BUG_ON(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		page = get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		if (!page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			efficeon_free_gatt_table(agp_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			clflush((char *)page+offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		efficeon_private.l1_table[index] = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		value = virt_to_phys((unsigned long *)page) | pati | present | index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		pci_write_config_dword(agp_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			EFFICEON_ATTPAGE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int i, count = mem->page_count, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned int *page, *last_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	const unsigned long clflush_mask = ~(clflush_chunk-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if ((pg_start + mem->page_count) > num_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (type != 0 || mem->type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	last_page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		int index = pg_start + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		unsigned long insert = efficeon_mask_memory(mem->pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		page = (unsigned int *) efficeon_private.l1_table[index >> 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		page += (index & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		*page = insert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		/* clflush is slow, so don't clflush until we have to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (last_page &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		    (((unsigned long)page^(unsigned long)last_page) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		     clflush_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			clflush(last_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		last_page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if ( last_page )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		clflush(last_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	int i, count = mem->page_count, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if ((pg_start + mem->page_count) > num_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (type != 0 || mem->type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		int index = pg_start + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		page += (index & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		*page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	agp_bridge->driver->tlb_flush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct agp_bridge_driver efficeon_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.aperture_sizes		= efficeon_generic_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.size_type		= LVL2_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.num_aperture_sizes	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.configure		= efficeon_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.fetch_size		= efficeon_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.cleanup		= efficeon_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.tlb_flush		= efficeon_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.mask_memory		= agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.masks			= efficeon_generic_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.agp_enable		= agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.cache_flush		= global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	// Efficeon-specific GATT table setup / populate / teardown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.create_gatt_table	= efficeon_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.free_gatt_table	= efficeon_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.insert_memory		= efficeon_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.remove_memory		= efficeon_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.cant_use_aperture	= false,	// true might be faster?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	// Generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.alloc_by_type		= agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.free_by_type		= agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.agp_alloc_page		= agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.agp_alloc_pages	= agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.agp_destroy_page	= agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.agp_destroy_pages	= agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int agp_efficeon_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			      const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	/* Probe for Efficeon controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (pdev->device != PCI_DEVICE_ID_EFFICEON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		    pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	bridge->driver = &efficeon_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	* If the device has not been properly setup, the following will catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	* the problem and should stop the system from crashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	* 20030610 - hamish@zot.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		printk(KERN_ERR PFX "Unable to Enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	* The following fixes the case where the BIOS has "forgotten" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	* provide an address range for the GART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	* 20030610 - hamish@zot.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	r = &pdev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (!r->start && r->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		if (pci_assign_resource(pdev, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			printk(KERN_ERR PFX "could not assign resource 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (cap_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 				bridge->capndx+PCI_AGP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 				&bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void agp_efficeon_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int agp_efficeon_suspend(struct pci_dev *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int agp_efficeon_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	printk(KERN_DEBUG PFX "agp_efficeon_resume()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return efficeon_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct pci_device_id agp_efficeon_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.class_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.vendor		= PCI_VENDOR_ID_TRANSMETA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.device		= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.subvendor	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.subdevice	= PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct pci_driver agp_efficeon_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.name		= "agpgart-efficeon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.id_table	= agp_efficeon_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.probe		= agp_efficeon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.remove		= agp_efficeon_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.suspend	= agp_efficeon_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.resume		= agp_efficeon_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int __init agp_efficeon_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	static int agp_initialised=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	if (agp_initialised == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	agp_initialised=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	return pci_register_driver(&agp_efficeon_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void __exit agp_efficeon_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	pci_unregister_driver(&agp_efficeon_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_init(agp_efficeon_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) module_exit(agp_efficeon_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_AUTHOR("Carlos Puchol <cpglinux@puchol.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_LICENSE("GPL and additional rights");