^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2001-2003 SuSE Labs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Distributed under the GNU public license, v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * It also includes support for the AMD 8151 AGP bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * although it doesn't actually do much, as all the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * work is done in the northbridge(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/page.h> /* PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/e820/api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/amd_nb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/gart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* NVIDIA K8 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NVIDIA_X86_64_0_APBASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NVIDIA_X86_64_1_APBASE1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NVIDIA_X86_64_1_APLIMIT1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NVIDIA_X86_64_1_APSIZE 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NVIDIA_X86_64_1_APBASE2 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NVIDIA_X86_64_1_APLIMIT2 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* ULi K8 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ULI_X86_64_BASE_ADDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ULI_X86_64_HTT_FEA_REG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ULI_X86_64_ENU_SCR_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct resource *aperture_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static bool __initdata agp_try_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int agp_bridges_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void amd64_tlbflush(struct agp_memory *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) amd_flush_garts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int i, j, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) long long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int mask_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct agp_bridge_data *bridge = mem->bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) num_entries = agp_num_entries();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (type != mem->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (mask_type != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Make sure we can fit the range in the gatt table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* FIXME: could wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (((unsigned long)pg_start + mem->page_count) > num_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) j = pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* gatt table should be empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (j < (pg_start + mem->page_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tmp = agp_bridge->driver->mask_memory(agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) page_to_phys(mem->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mask_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BUG_ON(tmp & 0xffffff0000000ffcULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pte = (tmp & 0x000000ff00000000ULL) >> 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pte |=(tmp & 0x00000000fffff000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pte |= GPTE_VALID | GPTE_COHERENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(pte, agp_bridge->gatt_table+j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) readl(agp_bridge->gatt_table+j); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) amd64_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This hack alters the order element according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * to the size of a long. It sucks. I totally disown this, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * though it does appear to work for the most part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct aper_size_info_32 amd64_aperture_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {32, 8192, 3+(sizeof(long)/8), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {64, 16384, 4+(sizeof(long)/8), 1<<1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {128, 32768, 5+(sizeof(long)/8), 1<<2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {512, 131072, 7+(sizeof(long)/8), 1<<3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Get the current Aperture size from the x86-64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Note, that there may be multiple x86-64's, but we just return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * the value from the first one we find. The set_size functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * keep the rest coherent anyway. Or at least should do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int amd64_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct aper_size_info_32 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev = node_to_amd_nb(0)->misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (dev==NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) temp = (temp & 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) values = A_SIZE_32(amd64_aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * In a multiprocessor x86-64 system, this function gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * called once for each CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 aperturebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 aper_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Address to map to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) aperturebase = (u64)tmp << 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enable_gart_translation(hammer, gatt_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return aper_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct aper_size_info_32 amd_8151_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int amd_8151_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!amd_nb_has_feature(AMD_NB_GART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Configure AGP regs in each x86-64 host bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; i < amd_nb_num(); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) agp_bridge->gart_bus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) amd_flush_garts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void amd64_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!amd_nb_has_feature(AMD_NB_GART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < amd_nb_num(); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pci_dev *dev = node_to_amd_nb(i)->misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* disable gart translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tmp &= ~GARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct agp_bridge_driver amd_8151_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .aperture_sizes = amd_8151_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .size_type = U32_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .configure = amd_8151_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .fetch_size = amd64_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .cleanup = amd64_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .tlb_flush = amd64_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .masks = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .create_gatt_table = agp_generic_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .free_gatt_table = agp_generic_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .insert_memory = amd64_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .remove_memory = agp_generic_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Some basic sanity checks for the aperture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int agp_aperture_valid(u64 aper, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!aperture_valid(aper, size, 32*1024*1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Request the Aperture. This catches cases when someone else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) already put a mapping in there - happens with some very broken BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) Maybe better to use pci_assign_resource/pci_enable_device instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) trusting the bridges? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!aperture_resource &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * W*s centric BIOS sometimes only set up the aperture in the AGP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * bridge, not the northbridge. On AMD64 this is handled early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * in aperture.c, but when IOMMU is not enabled or we run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * on a 32bit kernel this needs to be redone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Unfortunately it is impossible to fix the aperture here because it's too late
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * to allocate that much memory. But at least error out cleanly instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * crashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u64 aper, nb_aper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 nb_order, nb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u16 apsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) nb_order = (nb_order >> 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) nb_aper = (u64)nb_base << 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Northbridge seems to contain crap. Try the AGP bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pci_read_config_word(agp, cap+0x14, &apsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (apsize == 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) apsize &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Some BIOS use weird encodings not in the AGPv3 table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (apsize & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) apsize |= 0xf00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) order = 7 - hweight16(apsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) aper = pci_bus_address(agp, AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * On some sick chips APSIZE is 0. This means it wants 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * so let double check that order, and lets trust the AMD NB settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 32 << order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) order = nb_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (nb_order >= order) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) aper, 32 << order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gart_set_size_and_enable(nb, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (amd_cache_northbridges() < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!amd_nb_has_feature(AMD_NB_GART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (i = 0; i < amd_nb_num(); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct pci_dev *dev = node_to_amd_nb(i)->misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(&dev->dev, "no usable aperture found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #ifdef __x86_64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* should port this to i386 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Handle AMD 8151 quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) char *revstring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (pdev->revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 0x01: revstring="A0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case 0x02: revstring="A1"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 0x11: revstring="B0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 0x12: revstring="B1"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 0x13: revstring="B2"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case 0x14: revstring="B3"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) default: revstring="??"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Work around errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Chips before B2 stepping incorrectly reporting v3.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (pdev->revision < 0x13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bridge->major_version = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bridge->minor_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct aper_size_info_32 uli_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {256, 65536, 6, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {128, 32768, 5, 9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {64, 16384, 4, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {32, 8192, 3, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {16, 4096, 2, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {8, 2048, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {4, 1024, 0, 3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int uli_agp_init(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 httfea,baseaddr,enuscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct pci_dev *dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned size = amd64_fetch_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_info(&pdev->dev, "setting up ULi AGP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (dev1 == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_info(&pdev->dev, "can't find ULi secondary device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (uli_sizes[i].size == size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (i == ARRAY_SIZE(uli_sizes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_info(&pdev->dev, "no ULi size found for %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* shadow x86-64 registers into ULi registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &httfea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* if x86-64 aperture base is beyond 4G, exit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if ((httfea & 0x7fff) >> (32 - 25)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) httfea = (httfea& 0x7fff) << 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) baseaddr|= httfea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) enuscr= httfea+ (size * 1024 * 1024) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pci_dev_put(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct aper_size_info_32 nforce3_sizes[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {512, 131072, 7, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {256, 65536, 6, 0x00000008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {128, 32768, 5, 0x0000000C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {64, 16384, 4, 0x0000000E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {32, 8192, 3, 0x0000000F }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Handle shadow device of the Nvidia NForce3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int nforce3_agp_init(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 tmp, apbase, apbar, aplimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct pci_dev *dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned size = amd64_fetch_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (dev1 == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (nforce3_sizes[i].size == size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (i == ARRAY_SIZE(nforce3_sizes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tmp &= ~(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tmp |= nforce3_sizes[i].size_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* shadow x86-64 registers into NVIDIA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &apbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* if x86-64 aperture base is beyond 4G, exit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if ( (apbase & 0x7fff) >> (32 - 25) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_info(&pdev->dev, "aperture base > 4G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) apbase = (apbase & 0x7fff) << 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) apbar |= apbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) aplimit = apbase + (size * 1024 * 1024) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_dev_put(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int agp_amd64_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* The Highlander principle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (agp_bridges_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Could check for AGPv3 here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) amd8151_init(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pdev->vendor, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bridge->driver = &amd_8151_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (cache_nbs(pdev, cap_ptr) == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret = nforce3_agp_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (pdev->vendor == PCI_VENDOR_ID_AL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret = uli_agp_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) agp_bridges_found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void agp_amd64_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) release_mem_region(virt_to_phys(bridge->gatt_table_real),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) amd64_aperture_sizes[bridge->aperture_size_idx].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) agp_bridges_found--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pci_set_power_state(pdev, pci_choose_state(pdev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int agp_amd64_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) nforce3_agp_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return amd_8151_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const struct pci_device_id agp_amd64_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .vendor = PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .device = PCI_DEVICE_ID_AMD_8151_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* ULi M1689 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .vendor = PCI_VENDOR_ID_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .device = PCI_DEVICE_ID_AL_M1689,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* VIA K8T800Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* VIA K8T800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .device = PCI_DEVICE_ID_VIA_8385_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* VIA K8M800 / K8N800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .device = PCI_DEVICE_ID_VIA_8380_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* VIA K8M890 / K8N890 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .device = PCI_DEVICE_ID_VIA_VT3336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* VIA K8T890 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .device = PCI_DEVICE_ID_VIA_3238_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* VIA K8T800/K8M800/K8N800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .vendor = PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .device = PCI_DEVICE_ID_VIA_838X_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* NForce3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .vendor = PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .vendor = PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* SIS 755 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .vendor = PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .device = PCI_DEVICE_ID_SI_755,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* SIS 760 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .vendor = PCI_VENDOR_ID_SI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .device = PCI_DEVICE_ID_SI_760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* ALI/ULI M1695 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .vendor = PCI_VENDOR_ID_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .device = 0x1695,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct pci_device_id agp_amd64_pci_promisc_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { PCI_DEVICE_CLASS(0, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct pci_driver agp_amd64_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "agpgart-amd64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .id_table = agp_amd64_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .probe = agp_amd64_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .remove = agp_amd64_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .suspend = agp_amd64_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .resume = agp_amd64_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Not static due to IOMMU code calling it early. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int __init agp_amd64_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) err = pci_register_driver(&agp_amd64_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (agp_bridges_found == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!agp_try_unsupported && !agp_try_unsupported_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) printk(KERN_INFO PFX "No supported AGP bridge found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pci_unregister_driver(&agp_amd64_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* First check that we have at least one AMD64 NB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!amd_nb_num()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pci_unregister_driver(&agp_amd64_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Look for any AGP bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err = driver_attach(&agp_amd64_pci_driver.driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (err == 0 && agp_bridges_found == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pci_unregister_driver(&agp_amd64_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int __init agp_amd64_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (gart_iommu_aperture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return agp_bridges_found ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return agp_amd64_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void __exit agp_amd64_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (gart_iommu_aperture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (aperture_resource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) release_resource(aperture_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pci_unregister_driver(&agp_amd64_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) module_init(agp_amd64_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) module_exit(agp_amd64_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) MODULE_AUTHOR("Dave Jones, Andi Kleen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) module_param(agp_try_unsupported, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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