^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AMD K7 AGPGART routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/page-flags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "agp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AMD_MMBASE_BAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AMD_APSIZE 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AMD_MODECNTL 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AMD_MODECNTL2 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct pci_device_id agp_amdk7_pci_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct amd_page_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long *real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long __iomem *remapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct _amd_irongate_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) volatile u8 __iomem *registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct amd_page_map **gatt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int num_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) } amd_irongate_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int amd_create_page_map(struct amd_page_map *page_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (page_map->real == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) set_memory_uc((unsigned long)page_map->real, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) page_map->remapped = page_map->real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writel(agp_bridge->scratch_page, page_map->remapped+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) readl(page_map->remapped+i); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void amd_free_page_map(struct amd_page_map *page_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) set_memory_wb((unsigned long)page_map->real, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) free_page((unsigned long) page_map->real);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void amd_free_gatt_pages(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct amd_page_map **tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct amd_page_map *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tables = amd_irongate_private.gatt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (i = 0; i < amd_irongate_private.num_tables; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) entry = tables[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (entry != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (entry->real != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) amd_free_page_map(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) kfree(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) kfree(tables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) amd_irongate_private.gatt_pages = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int amd_create_gatt_pages(int nr_tables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct amd_page_map **tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct amd_page_map *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tables = kcalloc(nr_tables + 1, sizeof(struct amd_page_map *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (tables == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < nr_tables; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tables[i] = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (entry == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) retval = amd_create_page_map(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) amd_irongate_private.num_tables = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) amd_irongate_private.gatt_pages = tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) amd_free_gatt_pages();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Since we don't need contiguous memory we just try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * to get the gatt table once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GET_PAGE_DIR_IDX(addr)]->remapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int amd_create_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct aper_size_info_lvl2 *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct amd_page_map page_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long __iomem *cur_gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) value = A_SIZE_LVL2(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) retval = amd_create_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) retval = amd_create_gatt_pages(value->num_entries / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (retval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) amd_free_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) agp_bridge->gatt_table_real = (u32 *)page_dir.real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Get the address for the gart region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * This is a bus address even on the alpha, b/c its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * used to program the agp master not the cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) agp_bridge->gart_bus_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Calculate the agp offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) page_dir.remapped+GET_PAGE_DIR_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i = 0; i < value->num_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cur_gatt = GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int amd_free_gatt_table(struct agp_bridge_data *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct amd_page_map page_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) amd_free_gatt_pages();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) amd_free_page_map(&page_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int amd_irongate_fetch_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct aper_size_info_lvl2 *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) temp = (temp & 0x0000000e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (temp == values[i].size_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) agp_bridge->previous_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) agp_bridge->current_size = (void *) (values + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) agp_bridge->aperture_size_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return values[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int amd_irongate_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct aper_size_info_lvl2 *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) phys_addr_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) current_size = A_SIZE_LVL2(agp_bridge->current_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!amd_irongate_private.registers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Get the memory mapped registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!amd_irongate_private.registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Write out the address of the gatt table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Write the Sync register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Set indexing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Write the enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enable_reg = (enable_reg | 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Write out the size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Flush the tlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void amd_irongate_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct aper_size_info_lvl2 *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u16 enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enable_reg = (enable_reg & ~(0x0004));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Write back the previous size and disable gart translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iounmap((void __iomem *) amd_irongate_private.registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * This routine could be implemented by taking the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * written to the GATT, and flushing them individually. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * currently it just flushes the whole table. Which is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * more efficient, since agp_memory blocks can be a large number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void amd_irongate_tlbflush(struct agp_memory *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int i, j, num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned long __iomem *cur_gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if ((pg_start + mem->page_count) > num_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) j = pg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) while (j < (pg_start + mem->page_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cur_gatt = GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!mem->is_flushed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) global_cache_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mem->is_flushed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) cur_gatt = GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(agp_generic_mask_memory(agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) page_to_phys(mem->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mem->type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cur_gatt+GET_GATT_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) amd_irongate_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long __iomem *cur_gatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (type != mem->type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (i = pg_start; i < (mem->page_count + pg_start); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cur_gatt = GET_GATT(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) amd_irongate_tlbflush(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {2048, 524288, 0x0000000c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {1024, 262144, 0x0000000a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {512, 131072, 0x00000008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {256, 65536, 0x00000006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {128, 32768, 0x00000004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {64, 16384, 0x00000002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {32, 8192, 0x00000000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct gatt_mask amd_irongate_masks[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {.mask = 1, .type = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct agp_bridge_driver amd_irongate_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .aperture_sizes = amd_irongate_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .size_type = LVL2_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .num_aperture_sizes = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .needs_scratch_page = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .configure = amd_irongate_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .fetch_size = amd_irongate_fetch_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .cleanup = amd_irongate_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .tlb_flush = amd_irongate_tlbflush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .mask_memory = agp_generic_mask_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .masks = amd_irongate_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .agp_enable = agp_generic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .cache_flush = global_cache_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .create_gatt_table = amd_create_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .free_gatt_table = amd_free_gatt_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .insert_memory = amd_insert_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .remove_memory = amd_remove_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .alloc_by_type = agp_generic_alloc_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .free_by_type = agp_generic_free_by_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .agp_alloc_page = agp_generic_alloc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .agp_alloc_pages = agp_generic_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .agp_destroy_page = agp_generic_destroy_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .agp_destroy_pages = agp_generic_destroy_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .agp_type_to_mask_type = agp_generic_type_to_mask_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct agp_device_ids amd_agp_device_ids[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .chipset_name = "Irongate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .chipset_name = "761",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .chipset_name = "760MP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { }, /* dummy final entry, always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int agp_amdk7_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct agp_bridge_data *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) j = ent - agp_amdk7_pci_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_info(&pdev->dev, "AMD %s chipset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) amd_agp_device_ids[j].chipset_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bridge = agp_alloc_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bridge->driver = &amd_irongate_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bridge->dev_private_data = &amd_irongate_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bridge->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bridge->capndx = cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* 751 Errata (22564_B-1.PDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) system controller may experience noise due to strong drive strengths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct pci_dev *gfxcard=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cap_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) while (!cap_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!gfxcard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_info(&pdev->dev, "no AGP VGA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* With so many variants of NVidia cards, it's simpler just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) to blacklist them all, and then whitelist them as needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (if necessary at all). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) agp_bridge->flags |= AGP_ERRATA_1X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pci_dev_put(gfxcard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* 761 Errata (23613_F.pdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Revisions B0/B1 were a disaster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * erratum 45: Timing problem prevents fast writes -- Disable fast write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * With this lot disabled, we should prevent lockups. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (pdev->revision == 0x10 || pdev->revision == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) agp_bridge->flags = AGP_ERRATA_FASTWRITES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) agp_bridge->flags |= AGP_ERRATA_SBA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) agp_bridge->flags |= AGP_ERRATA_1X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Fill in the mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bridge->capndx+PCI_AGP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &bridge->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pci_set_drvdata(pdev, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return agp_add_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void agp_amdk7_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) agp_remove_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) agp_put_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_set_power_state(pdev, pci_choose_state(pdev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int agp_amdk7_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return amd_irongate_driver.configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* must be the same order as name table above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct pci_device_id agp_amdk7_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .vendor = PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .vendor = PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .class = (PCI_CLASS_BRIDGE_HOST << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .vendor = PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct pci_driver agp_amdk7_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "agpgart-amdk7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .id_table = agp_amdk7_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .probe = agp_amdk7_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .remove = agp_amdk7_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .suspend = agp_amdk7_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .resume = agp_amdk7_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int __init agp_amdk7_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (agp_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return pci_register_driver(&agp_amdk7_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void __exit agp_amdk7_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pci_unregister_driver(&agp_amdk7_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) module_init(agp_amdk7_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_exit(agp_amdk7_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_LICENSE("GPL and additional rights");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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