Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AGPGART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2004 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2002-2004 Dave Jones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1999 Jeff Hartmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1999 Precision Insight, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 1999 Xi Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * The above copyright notice and this permission notice shall be included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef _AGP_BACKEND_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define _AGP_BACKEND_PRIV_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/agp.h>	/* for flush_agp_cache() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PFX "agpgart: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) //#define AGP_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifdef AGP_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __func__ , ## y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DBG(x,y...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) extern struct agp_bridge_data *agp_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) enum aper_size_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	U8_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	U16_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	U32_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	LVL2_APER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	FIXED_APER_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct gatt_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* totally device specific, for integrated chipsets that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * might have different types of memory masks.  For other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * devices this will probably be ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AGP_PAGE_DESTROY_UNMAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AGP_PAGE_DESTROY_FREE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct aper_size_info_8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8 size_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct aper_size_info_16 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u16 size_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct aper_size_info_32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 size_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct aper_size_info_lvl2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 size_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) struct aper_size_info_fixed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int page_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) struct agp_bridge_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	const void *aperture_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int num_aperture_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	enum aper_size_type size_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool cant_use_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	bool needs_scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	const struct gatt_mask *masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int (*fetch_size)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int (*configure)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void (*agp_enable)(struct agp_bridge_data *, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	void (*cleanup)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	void (*tlb_flush)(struct agp_memory *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	void (*cache_flush)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int (*create_gatt_table)(struct agp_bridge_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int (*free_gatt_table)(struct agp_bridge_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int (*insert_memory)(struct agp_memory *, off_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int (*remove_memory)(struct agp_memory *, off_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct agp_memory *(*alloc_by_type) (size_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	void (*free_by_type)(struct agp_memory *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct page *(*agp_alloc_page)(struct agp_bridge_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	void (*agp_destroy_page)(struct page *, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	void (*agp_destroy_pages)(struct agp_memory *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct agp_bridge_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	const struct agp_version *version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	const struct agp_bridge_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	const struct vm_operations_struct *vm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	void *previous_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	void *current_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	void *dev_private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 __iomem *gatt_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 *gatt_table_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned long scratch_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct page *scratch_page_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	dma_addr_t scratch_page_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned long gart_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long gatt_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	enum chipset_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned long *key_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	atomic_t current_memory_agp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	atomic_t agp_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int max_memory_agp;	/* in number of pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int aperture_size_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int capndx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	char major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	char minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 apbase_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* list of agp_memory mapped to the aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct list_head mapped_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	spinlock_t mapped_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define KB(x)	((x) * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MB(x)	(KB (KB (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GB(x)	(MB (KB (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define A_SIZE_8(x)	((struct aper_size_info_8 *) x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define A_SIZE_16(x)	((struct aper_size_info_16 *) x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define A_SIZE_32(x)	((struct aper_size_info_32 *) x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define A_SIZE_LVL2(x)	((struct aper_size_info_lvl2 *) x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define A_SIZE_FIX(x)	((struct aper_size_info_fixed *) x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define A_IDX8(bridge)	(A_SIZE_8((bridge)->driver->aperture_sizes) + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define A_IDX16(bridge)	(A_SIZE_16((bridge)->driver->aperture_sizes) + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define A_IDX32(bridge)	(A_SIZE_32((bridge)->driver->aperture_sizes) + i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAXKEY		(4096 * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PGE_EMPTY(b, p)	(!(p) || (p) == (unsigned long) (b)->scratch_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct agp_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned short device_id; /* first, to make table easier to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	enum chipset_type chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	const char *chipset_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int (*chipset_setup) (struct pci_dev *pdev);	/* used to override generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Driver registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct agp_bridge_data *agp_alloc_bridge(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void agp_put_bridge(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int agp_add_bridge(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void agp_remove_bridge(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Frontend routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int agp_frontend_initialize(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void agp_frontend_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Generic routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct agp_memory *agp_create_memory(int scratch_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void agp_generic_free_by_type(struct agp_memory *curr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct page *agp_generic_alloc_page(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			    struct agp_memory *memory, size_t page_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void agp_generic_destroy_page(struct page *page, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void agp_generic_destroy_pages(struct agp_memory *memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void agp_free_key(int key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int agp_num_entries(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void agp_device_command(u32 command, bool agp_v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int agp_3_5_enable(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void global_cache_flush(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void get_agp_version(struct agp_bridge_data *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				      dma_addr_t phys, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				  int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* generic functions for user-populated AGP memory types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct agp_memory *agp_generic_alloc_user(size_t page_count, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void agp_alloc_page_array(size_t size, struct agp_memory *mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void agp_free_page_array(struct agp_memory *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	kvfree(mem->pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* generic routines for agp>=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int agp3_generic_fetch_size(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void agp3_generic_tlbflush(struct agp_memory *mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int agp3_generic_configure(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void agp3_generic_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* aperture sizes have been standardised since v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AGP_GENERIC_SIZES_ENTRIES 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) extern const struct aper_size_info_16 agp3_generic_sizes[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) extern int agp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) extern int agp_try_unsupported_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Chipset independent registers (from AGP Spec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AGP_APBASE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AGP_APERTURE_BAR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AGPSTAT		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AGPCMD		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AGPNISTAT	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AGPCTRL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AGPAPSIZE	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AGPNEPG		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AGPGARTLO	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AGPGARTHI	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AGPNICMD	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AGP_MAJOR_VERSION_SHIFT	(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AGP_MINOR_VERSION_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AGPSTAT_RQ_DEPTH	(0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AGPSTAT_RQ_DEPTH_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AGPSTAT_CAL_MASK	(1<<12|1<<11|1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AGPSTAT_ARQSZ		(1<<15|1<<14|1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AGPSTAT_ARQSZ_SHIFT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AGPSTAT_SBA		(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AGPSTAT_AGP_ENABLE	(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AGPSTAT_FW		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AGPSTAT_MODE_3_0	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AGPSTAT2_1X		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AGPSTAT2_2X		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AGPSTAT2_4X		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AGPSTAT3_RSVD		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AGPSTAT3_8X		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AGPSTAT3_4X		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AGPCTRL_APERENB		(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define AGPCTRL_GTLBEN		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AGP2_RESERVED_MASK 0x00fffcc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AGP3_RESERVED_MASK 0x00ff00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AGP_ERRATA_FASTWRITES 1<<0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AGP_ERRATA_SBA	 1<<1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AGP_ERRATA_1X 1<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif	/* _AGP_BACKEND_PRIV_H */