^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* System Bus Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNIPHIER_SBC_NR_BANKS 8 /* number of banks (chip select) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct uniphier_system_bus_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct uniphier_system_bus_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int uniphier_system_bus_add_bank(struct uniphier_system_bus_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int bank, u32 addr, u64 paddr, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u64 end, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dev_dbg(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bank, addr, paddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (bank >= ARRAY_SIZE(priv->bank)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_err(priv->dev, "unsupported bank number %d\n", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (priv->bank[bank].base || priv->bank[bank].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "range for bank %d has already been specified\n", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (paddr > U32_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_err(priv->dev, "base address %llx is too high\n", paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) end = paddr + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (addr > paddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "base %08x cannot be mapped to %08llx of parent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) addr, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) paddr -= addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) paddr = round_down(paddr, 0x00020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) end = round_up(end, 0x00020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (end > U32_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(priv->dev, "end address %08llx is too high\n", end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mask = paddr ^ (end - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mask = roundup_pow_of_two(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) paddr = round_down(paddr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) end = round_up(end, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) priv->bank[bank].base = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) priv->bank[bank].end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bank, priv->bank[bank].base, priv->bank[bank].end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int uniphier_system_bus_check_overlap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct uniphier_system_bus_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (priv->bank[i].end > priv->bank[j].base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) priv->bank[i].base < priv->bank[j].end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "region overlap between bank%d and bank%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void uniphier_system_bus_check_boot_swap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct uniphier_system_bus_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int is_swapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(priv->dev, "Boot Swap: %s\n", is_swapped ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * If BOOT_SWAP was asserted on power-on-reset, the CS0 and CS1 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * swapped. In this case, bank0 and bank1 should be swapped as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (is_swapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) swap(priv->bank[0], priv->bank[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void uniphier_system_bus_set_reg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const struct uniphier_system_bus_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 base, end, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) base = priv->bank[i].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) end = priv->bank[i].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (base == end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * If SBC_BASE0 or SBC_BASE1 is set to zero, the access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * to anywhere in the system bus space is routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * bank 0 (if boot swap if off) or bank 1 (if boot swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * if on). It means that CPUs cannot get access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * bank 2 or later. In other words, bank 0/1 cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * be disabled even if its bank_enable bits is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * This seems odd, but it is how this hardware goes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * As a workaround, dummy data (0xffffffff) should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * set when the bank 0/1 is unused. As for bank 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * later, they can be simply disable by clearing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * bank_enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (i < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = UNIPHIER_SBC_BASE_DUMMY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mask = base ^ (end - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = base & 0xfffe0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val |= (~mask >> 16) & 0xfffe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= UNIPHIER_SBC_BASE_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int uniphier_system_bus_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct uniphier_system_bus_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const __be32 *ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 cells, addr, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u64 paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int pna, bank, rlen, rone, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) priv->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(priv->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return PTR_ERR(priv->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pna = of_n_addr_cells(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = of_property_read_u32(dev->of_node, "#address-cells", &cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(dev, "failed to get #address-cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (cells != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dev, "#address-cells must be 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = of_property_read_u32(dev->of_node, "#size-cells", &cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(dev, "failed to get #size-cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (cells != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(dev, "#size-cells must be 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ranges = of_get_property(dev->of_node, "ranges", &rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(dev, "failed to get ranges property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rlen /= sizeof(*ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rone = pna + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (; rlen >= rone; rlen -= rone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bank = be32_to_cpup(ranges++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) addr = be32_to_cpup(ranges++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) paddr = of_translate_address(dev->of_node, ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (paddr == OF_BAD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ranges += pna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) size = be32_to_cpup(ranges++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = uniphier_system_bus_add_bank(priv, bank, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) paddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = uniphier_system_bus_check_overlap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uniphier_system_bus_check_boot_swap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uniphier_system_bus_set_reg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Now, the bus is configured. Populate platform_devices below it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return of_platform_default_populate(dev->of_node, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uniphier_system_bus_set_reg(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id uniphier_system_bus_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .compatible = "socionext,uniphier-system-bus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DEVICE_TABLE(of, uniphier_system_bus_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct platform_driver uniphier_system_bus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .probe = uniphier_system_bus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "uniphier-system-bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .of_match_table = uniphier_system_bus_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .pm = &uniphier_system_bus_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) module_platform_driver(uniphier_system_bus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DESCRIPTION("UniPhier System Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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