^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * NBUS driver for TS-4600 based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016 - Savoir-faire Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver implements a GPIOs bit-banged bus, called the NBUS by Technologic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Systems. It is used to communicate with the peripherals in the FPGA on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * TS-4600 SoM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ts-nbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TS_NBUS_DIRECTION_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TS_NBUS_DIRECTION_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TS_NBUS_WRITE_ADR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TS_NBUS_WRITE_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ts_nbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct gpio_descs *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct gpio_desc *csn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_desc *txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct gpio_desc *strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct gpio_desc *ale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_desc *rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * request all gpios required by the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int ts_nbus_init_pdata(struct platform_device *pdev, struct ts_nbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *ts_nbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ts_nbus->data = devm_gpiod_get_array(&pdev->dev, "ts,data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (IS_ERR(ts_nbus->data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dev_err(&pdev->dev, "failed to retrieve ts,data-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return PTR_ERR(ts_nbus->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ts_nbus->csn = devm_gpiod_get(&pdev->dev, "ts,csn", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (IS_ERR(ts_nbus->csn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(&pdev->dev, "failed to retrieve ts,csn-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return PTR_ERR(ts_nbus->csn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ts_nbus->txrx = devm_gpiod_get(&pdev->dev, "ts,txrx", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (IS_ERR(ts_nbus->txrx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_err(&pdev->dev, "failed to retrieve ts,txrx-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return PTR_ERR(ts_nbus->txrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ts_nbus->strobe = devm_gpiod_get(&pdev->dev, "ts,strobe", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (IS_ERR(ts_nbus->strobe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_err(&pdev->dev, "failed to retrieve ts,strobe-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return PTR_ERR(ts_nbus->strobe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ts_nbus->ale = devm_gpiod_get(&pdev->dev, "ts,ale", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (IS_ERR(ts_nbus->ale)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(&pdev->dev, "failed to retrieve ts,ale-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return PTR_ERR(ts_nbus->ale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ts_nbus->rdy = devm_gpiod_get(&pdev->dev, "ts,rdy", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (IS_ERR(ts_nbus->rdy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(&pdev->dev, "failed to retrieve ts,rdy-gpio from dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return PTR_ERR(ts_nbus->rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * the data gpios are used for reading and writing values, their directions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * should be adjusted accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void ts_nbus_set_direction(struct ts_nbus *ts_nbus, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (direction == TS_NBUS_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) gpiod_direction_input(ts_nbus->data->desc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* when used as output the default state of the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * lines are set to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) gpiod_direction_output(ts_nbus->data->desc[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * reset the bus in its initial state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * The data, csn, strobe and ale lines must be zero'ed to let the FPGA knows a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * new transaction can be process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void ts_nbus_reset_bus(struct ts_nbus *ts_nbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DECLARE_BITMAP(values, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) values[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) gpiod_set_array_value_cansleep(8, ts_nbus->data->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ts_nbus->data->info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gpiod_set_value_cansleep(ts_nbus->csn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gpiod_set_value_cansleep(ts_nbus->strobe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gpiod_set_value_cansleep(ts_nbus->ale, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * let the FPGA knows it can process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void ts_nbus_start_transaction(struct ts_nbus *ts_nbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) gpiod_set_value_cansleep(ts_nbus->strobe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * read a byte value from the data gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * return 0 on success or negative errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int ts_nbus_read_byte(struct ts_nbus *ts_nbus, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct gpio_descs *gpios = ts_nbus->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = gpiod_get_value_cansleep(gpios->desc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *val |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * set the data gpios accordingly to the byte value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void ts_nbus_write_byte(struct ts_nbus *ts_nbus, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct gpio_descs *gpios = ts_nbus->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DECLARE_BITMAP(values, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) values[0] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gpiod_set_array_value_cansleep(8, gpios->desc, gpios->info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * reading the bus consists of resetting the bus, then notifying the FPGA to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * send the data in the data gpios and return the read value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * return 0 on success or negative errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int ts_nbus_read_bus(struct ts_nbus *ts_nbus, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ts_nbus_reset_bus(ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ts_nbus_start_transaction(ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ts_nbus_read_byte(ts_nbus, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * writing to the bus consists of resetting the bus, then define the type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * command (address/value), write the data and notify the FPGA to retrieve the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * value in the data gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void ts_nbus_write_bus(struct ts_nbus *ts_nbus, int cmd, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ts_nbus_reset_bus(ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (cmd == TS_NBUS_WRITE_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gpiod_set_value_cansleep(ts_nbus->ale, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ts_nbus_write_byte(ts_nbus, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ts_nbus_start_transaction(ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * read the value in the FPGA register at the given address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * return 0 on success or negative errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ts_nbus_read(struct ts_nbus *ts_nbus, u8 adr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* bus access must be atomic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mutex_lock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* set the bus in read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gpiod_set_value_cansleep(ts_nbus->txrx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_ADR, adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* set the data gpios direction as input before reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ts_nbus_set_direction(ts_nbus, TS_NBUS_DIRECTION_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* reading value MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* read a byte from the bus, leave on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = ts_nbus_read_bus(ts_nbus, &byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* append the byte read to the final value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *val |= byte << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) gpiod_set_value_cansleep(ts_nbus->csn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = gpiod_get_value_cansleep(ts_nbus->rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } while (ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* restore the data gpios direction as output after reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ts_nbus_set_direction(ts_nbus, TS_NBUS_DIRECTION_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mutex_unlock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) EXPORT_SYMBOL_GPL(ts_nbus_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * write the desired value in the FPGA register at the given address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ts_nbus_write(struct ts_nbus *ts_nbus, u8 adr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* bus access must be atomic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mutex_lock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* set the bus in write mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gpiod_set_value_cansleep(ts_nbus->txrx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_ADR, adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* writing value MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ts_nbus_write_bus(ts_nbus, TS_NBUS_WRITE_VAL, (u8)(val >> (i * 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) gpiod_set_value_cansleep(ts_nbus->csn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (gpiod_get_value_cansleep(ts_nbus->rdy) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) gpiod_set_value_cansleep(ts_nbus->csn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) gpiod_set_value_cansleep(ts_nbus->csn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_unlock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EXPORT_SYMBOL_GPL(ts_nbus_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int ts_nbus_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pwm_args pargs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ts_nbus *ts_nbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ts_nbus = devm_kzalloc(dev, sizeof(*ts_nbus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!ts_nbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mutex_init(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = ts_nbus_init_pdata(pdev, ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pwm = devm_pwm_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (IS_ERR(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = PTR_ERR(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(dev, "unable to request PWM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pwm_get_args(pwm, &pargs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!pargs.period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(&pdev->dev, "invalid PWM period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * FIXME: pwm_apply_args() should be removed when switching to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * the atomic PWM API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pwm_apply_args(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = pwm_config(pwm, pargs.period, pargs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * we can now start the FPGA and populate the peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pwm_enable(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ts_nbus->pwm = pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * let the child nodes retrieve this instance of the ts-nbus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_set_drvdata(dev, ts_nbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_info(dev, "initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int ts_nbus_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ts_nbus *ts_nbus = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* shutdown the FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mutex_lock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pwm_disable(ts_nbus->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mutex_unlock(&ts_nbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct of_device_id ts_nbus_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .compatible = "technologic,ts-nbus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DEVICE_TABLE(of, ts_nbus_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct platform_driver ts_nbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .probe = ts_nbus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .remove = ts_nbus_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .name = "ts_nbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .of_match_table = ts_nbus_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) module_platform_driver(ts_nbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_ALIAS("platform:ts_nbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_DESCRIPTION("Technologic Systems NBUS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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