^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ti-sysc.c - Texas Instruments sysc interconnect target driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/timekeeping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/ti-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <dt-bindings/bus/ti-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DIS_ISP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DIS_IVA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DIS_SGX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_MODULE_SOFTRESET_WAIT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum sysc_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SOC_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SOC_2420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SOC_2430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SOC_3430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SOC_3630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SOC_4430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SOC_4460,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SOC_4470,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SOC_5430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SOC_AM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SOC_AM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SOC_DRA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct sysc_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sysc_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct sysc_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long general_purpose:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum sysc_soc soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mutex list_lock; /* disabled and restored modules list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct list_head disabled_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct list_head restored_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum sysc_clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SYSC_FCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SYSC_ICK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SYSC_OPTFCK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SYSC_OPTFCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SYSC_OPTFCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SYSC_OPTFCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SYSC_OPTFCK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SYSC_OPTFCK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SYSC_OPTFCK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SYSC_OPTFCK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SYSC_MAX_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct sysc_soc_info *sysc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char * const reg_names[] = { "rev", "sysc", "syss", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const clock_names[SYSC_MAX_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "opt5", "opt6", "opt7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SYSC_IDLEMODE_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SYSC_CLOCKACTIVITY_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct sysc - TI sysc interconnect target module registers and capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @dev: struct device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @module_pa: physical address of the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @module_size: size of the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @module_va: virtual address of the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @offsets: register offsets from module base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @mdata: ti-sysc to hwmod translation data for a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @clocks: clocks used by the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @clock_roles: clock role names for the found clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @nr_clocks: number of clocks used by the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @rsts: resets used by the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @legacy_mode: configured for legacy mode if set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @cap: interconnect target module capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @cfg: interconnect target module configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @cookie: data used by legacy platform callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @name: name if available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @revision: interconnect target module revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @reserved: target module is reserved and already in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @enabled: sysc runtime enabled status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @needs_resume: runtime resume needed on resume from suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @child_needs_resume: runtime resume needed for child on resume from suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @disable_on_idle: status flag used for disabling modules with resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @idle_work: work structure used to perform delayed idle on a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @pre_reset_quirk: module specific pre-reset quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @post_reset_quirk: module specific post-reset quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @reset_done_quirk: module specific reset done quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @module_enable_quirk: module specific enable quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @module_disable_quirk: module specific disable quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @module_unlock_quirk: module specific sysconfig unlock quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @module_lock_quirk: module specific sysconfig lock quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sysc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u64 module_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 module_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void __iomem *module_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int offsets[SYSC_MAX_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ti_sysc_module_data *mdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct clk **clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char **clock_roles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int nr_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct reset_control *rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const char *legacy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct sysc_capabilities *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct sysc_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ti_sysc_cookie cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int needs_resume:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int child_needs_resume:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct delayed_work idle_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void (*pre_reset_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void (*post_reset_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void (*reset_done_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void (*module_enable_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void (*module_disable_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void (*module_unlock_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void (*module_lock_quirk)(struct sysc *sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool is_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void sysc_write(struct sysc *ddata, int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writew_relaxed(value & 0xffff, ddata->module_va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Only i2c revision has LO and HI register with stride of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ddata->offsets[SYSC_REVISION] >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) offset == ddata->offsets[SYSC_REVISION]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 hi = value >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writew_relaxed(hi, ddata->module_va + offset + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel_relaxed(value, ddata->module_va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static u32 sysc_read(struct sysc *ddata, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = readw_relaxed(ddata->module_va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Only i2c revision has LO and HI register with stride of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ddata->offsets[SYSC_REVISION] >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) offset == ddata->offsets[SYSC_REVISION]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val |= tmp << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return readl_relaxed(ddata->module_va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static bool sysc_opt_clks_needed(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u32 sysc_read_revision(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int offset = ddata->offsets[SYSC_REVISION];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return sysc_read(ddata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static u32 sysc_read_sysconfig(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int offset = ddata->offsets[SYSC_SYSCONFIG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return sysc_read(ddata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static u32 sysc_read_sysstatus(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int offset = ddata->offsets[SYSC_SYSSTATUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return sysc_read(ddata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int sysc_poll_reset_sysstatus(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int error, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 syss_done, rstval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) syss_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) syss_done = ddata->cfg.syss_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (likely(!timekeeping_suspended)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rstval, (rstval & ddata->cfg.syss_mask) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) retries = MAX_MODULE_SOFTRESET_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rstval = sysc_read_sysstatus(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if ((rstval & ddata->cfg.syss_mask) == syss_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) udelay(2); /* Account for udelay flakeyness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int sysc_poll_reset_sysconfig(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int error, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 sysc_mask, rstval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sysc_mask = BIT(ddata->cap->regbits->srst_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (likely(!timekeeping_suspended)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rstval, !(rstval & sysc_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 100, MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) retries = MAX_MODULE_SOFTRESET_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rstval = sysc_read_sysconfig(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!(rstval & sysc_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) udelay(2); /* Account for udelay flakeyness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Poll on reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int sysc_wait_softreset(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int syss_offset, error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ddata->cap->regbits->srst_shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) syss_offset = ddata->offsets[SYSC_SYSSTATUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (syss_offset >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) error = sysc_poll_reset_sysstatus(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) error = sysc_poll_reset_sysconfig(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int sysc_add_named_clock_from_child(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const char *optfck_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct clk_lookup *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) n = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) n = optfck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Does the clock alias already exist? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clock = of_clk_get_by_name(np, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_put(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) child = of_get_next_available_child(np, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clock = devm_get_clk_from_child(ddata->dev, child, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * limit for clk_get(). If cl ever needs to be freed, it should be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * with clkdev_drop().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cl->con_id = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cl->dev_id = dev_name(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cl->clk = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clkdev_add(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_put(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const char *optfck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int error, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ddata->nr_clocks < SYSC_OPTFCK0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) index = SYSC_OPTFCK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) index = ddata->nr_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) optfck_name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) optfck_name = clock_names[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ddata->clock_roles[index] = optfck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ddata->nr_clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int sysc_get_one_clock(struct sysc *ddata, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int error, i, index = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!strncmp(clock_names[SYSC_FCK], name, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) index = SYSC_FCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) else if (!strncmp(clock_names[SYSC_ICK], name, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) index = SYSC_ICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!ddata->clocks[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(ddata->dev, "clock %s not added\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ddata->clocks[index] = devm_clk_get(ddata->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (IS_ERR(ddata->clocks[index])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(ddata->dev, "clock get error for %s: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) name, PTR_ERR(ddata->clocks[index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return PTR_ERR(ddata->clocks[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) error = clk_prepare(ddata->clocks[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(ddata->dev, "clock prepare error for %s: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) name, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int sysc_get_clocks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int nr_fck = 0, nr_ick = 0, i, error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ddata->clock_roles = devm_kcalloc(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SYSC_MAX_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) sizeof(*ddata->clock_roles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!ddata->clock_roles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) of_property_for_each_string(np, "clock-names", prop, name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!strncmp(clock_names[SYSC_FCK], name, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) nr_fck++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!strncmp(clock_names[SYSC_ICK], name, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) nr_ick++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ddata->clock_roles[ddata->nr_clocks] = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ddata->nr_clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ddata->nr_clocks < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) error = sysc_init_ext_opt_clock(ddata, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(ddata->dev, "too many clocks for %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (nr_fck > 1 || nr_ick > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Always add a slot for main clocks fck and ick even if unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!nr_fck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ddata->nr_clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!nr_ick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ddata->nr_clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ddata->clocks = devm_kcalloc(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ddata->nr_clocks, sizeof(*ddata->clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!ddata->clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) const char *name = ddata->clock_roles[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) error = sysc_get_one_clock(ddata, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int sysc_enable_main_clocks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int i, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!ddata->clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for (i = 0; i < SYSC_OPTFCK0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Main clocks may not have ick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) error = clk_enable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i--; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Main clocks may not have ick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clk_disable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void sysc_disable_main_clocks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!ddata->clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (i = 0; i < SYSC_OPTFCK0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk_disable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int sysc_enable_opt_clocks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Assume no holes for opt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) error = clk_enable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) for (i--; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_disable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static void sysc_disable_opt_clocks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) clock = ddata->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Assume no holes for opt clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (IS_ERR_OR_NULL(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_disable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void sysc_clkdm_deny_idle(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct ti_sysc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (pdata && pdata->clkdm_deny_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void sysc_clkdm_allow_idle(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct ti_sysc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (pdata && pdata->clkdm_allow_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * sysc_init_resets - init rstctrl reset line if configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * See sysc_rstctrl_reset_deassert().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int sysc_init_resets(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ddata->rsts =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return PTR_ERR_OR_ZERO(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * sysc_parse_and_check_child_range - parses module IO region from ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * In general we only need rev, syss, and sysc registers and not the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * module range. But we do want the offsets for these registers from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * module base. This allows us to check them against the legacy hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * platform data. Let's also check the ranges are configured properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int sysc_parse_and_check_child_range(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) const __be32 *ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 nr_addr, nr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int len, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ranges = of_get_property(np, "ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(ddata->dev, "missing ranges for %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) len /= sizeof(*ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (len < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) error = of_property_read_u32(np, "#address-cells", &nr_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) error = of_property_read_u32(np, "#size-cells", &nr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (nr_addr != 1 || nr_size != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ranges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ddata->module_pa = of_translate_address(np, ranges++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ddata->module_size = be32_to_cpup(ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Interconnect instances to probe before l4_per instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static struct resource early_bus_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* am3/4 l4_wkup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* omap4/5 and dra7 l4_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* omap4 l4_wkup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* omap5 and dra7 l4_wkup without dra7 dcan segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static atomic_t sysc_defer = ATOMIC_INIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * sysc_defer_non_critical - defer non_critical interconnect probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * We want to probe l4_cfg and l4_wkup interconnect instances before any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * l4_per instances as l4_per instances depend on resources on l4_cfg and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * l4_wkup interconnects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int sysc_defer_non_critical(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!atomic_read(&sysc_defer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) res = &early_bus_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ddata->module_pa >= res->start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ddata->module_pa <= res->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) atomic_set(&sysc_defer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) atomic_dec_if_positive(&sysc_defer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct device_node *stdout_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void sysc_init_stdout_path(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) const char *uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (IS_ERR(stdout_path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (stdout_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) np = of_find_node_by_path("/chosen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uart = of_get_property(np, "stdout-path", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!uart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) np = of_find_node_by_path(uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) stdout_path = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) stdout_path = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void sysc_check_quirk_stdout(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sysc_init_stdout_path(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (np != stdout_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SYSC_QUIRK_NO_RESET_ON_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * sysc_check_one_child - check child configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * @np: child device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Let's avoid messy situations where we have new interconnect target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * node but children have "ti,hwmods". These belong to the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * target node and are managed by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void sysc_check_one_child(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) name = of_get_property(np, "ti,hwmods", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (name && !of_device_is_compatible(np, "ti,sysc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_warn(ddata->dev, "really a child ti,hwmods property?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) sysc_check_quirk_stdout(ddata, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sysc_parse_dts_quirks(ddata, np, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void sysc_check_children(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) for_each_child_of_node(ddata->dev->of_node, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) sysc_check_one_child(ddata, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * So far only I2C uses 16-bit read access with clockactivity with revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * in two registers with stride of 4. We can detect this based on the rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * register size to configure things far enough to be able to properly read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * the revision register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (resource_size(res) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * sysc_parse_one - parses the interconnect target module registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * @reg: register to parse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case SYSC_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case SYSC_SYSCONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case SYSC_SYSSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) name = reg_names[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) res = platform_get_resource_byname(to_platform_device(ddata->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) IORESOURCE_MEM, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ddata->offsets[reg] = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ddata->offsets[reg] = res->start - ddata->module_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (reg == SYSC_REVISION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) sysc_check_quirk_16bit(ddata, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int sysc_parse_registers(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int i, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) for (i = 0; i < SYSC_MAX_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) error = sysc_parse_one(ddata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * sysc_check_registers - check for misconfigured register overlaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int sysc_check_registers(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int i, j, nr_regs = 0, nr_matches = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) for (i = 0; i < SYSC_MAX_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ddata->offsets[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ddata->offsets[i] > (ddata->module_size - 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(ddata->dev, "register outside module range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for (j = 0; j < SYSC_MAX_REGS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ddata->offsets[j] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ddata->offsets[i] == ddata->offsets[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) nr_matches++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) nr_regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (nr_matches > nr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(ddata->dev, "overlapping registers: (%i/%i)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) nr_regs, nr_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * syc_ioremap - ioremap register space for the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * Note that the interconnect target module registers can be anywhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * within the interconnect target module range. For example, SGX has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * them at offset 0x1fc00 in the 32MB module address space. And cpsw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * has them at offset 0x1200 in the CPSW_WR child. Usually the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * the interconnect target module registers are at the beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * the module range though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int sysc_ioremap(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ddata->offsets[SYSC_REVISION] < 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ddata->offsets[SYSC_SYSCONFIG] < 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ddata->offsets[SYSC_SYSSTATUS] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) size = ddata->module_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) size = max3(ddata->offsets[SYSC_REVISION],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ddata->offsets[SYSC_SYSCONFIG],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ddata->offsets[SYSC_SYSSTATUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (size < SZ_1K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) size = SZ_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if ((size + sizeof(u32)) > ddata->module_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) size = ddata->module_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ddata->module_va = devm_ioremap(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ddata->module_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) size + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!ddata->module_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * sysc_map_and_check_registers - ioremap and check device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int sysc_map_and_check_registers(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) error = sysc_parse_and_check_child_range(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) error = sysc_defer_non_critical(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) sysc_check_children(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) error = sysc_parse_registers(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) error = sysc_ioremap(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) error = sysc_check_registers(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * sysc_show_rev - read and show interconnect target module revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * @bufp: buffer to print the information to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int sysc_show_rev(char *bufp, struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ddata->offsets[SYSC_REVISION] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return sprintf(bufp, ":NA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) len = sprintf(bufp, ":%08x", ddata->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int sysc_show_reg(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) char *bufp, enum sysc_registers reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (ddata->offsets[reg] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return sprintf(bufp, ":NA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return sprintf(bufp, ":%x", ddata->offsets[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int sysc_show_name(char *bufp, struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (!ddata->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return sprintf(bufp, ":%s", ddata->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * sysc_show_registers - show information about interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void sysc_show_registers(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) char buf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) char *bufp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 0; i < SYSC_MAX_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) bufp += sysc_show_reg(ddata, bufp, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) bufp += sysc_show_rev(bufp, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) bufp += sysc_show_name(bufp, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_dbg(ddata->dev, "%llx:%x%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ddata->module_pa, ddata->module_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * sysc_write_sysconfig - handle sysconfig quirks for register write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * @value: register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ddata->module_unlock_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ddata->module_unlock_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ddata->module_lock_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ddata->module_lock_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define SYSC_CLOCACT_ICK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int sysc_enable_module(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) const struct sysc_regbits *regbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 reg, idlemodes, best_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * Some modules like DSS reset automatically on idle. Enable optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * reset clocks and wait for OCP softreset to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) error = sysc_enable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev_err(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "Optional clocks failed for enable: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * Some modules like i2c and hdq1w have unusable reset status unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * the module reset quirk is enabled. Skip status check on enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) error = sysc_wait_softreset(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_warn(ddata->dev, "OCP softreset timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Some subsystem private interconnects, like DSS top level module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * need only the automatic OCP softreset handling with no sysconfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * register bits to configure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) regbits = ddata->cap->regbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (regbits->clkact_shift >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Set SIDLE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) idlemodes = ddata->cfg.sidlemodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!idlemodes || regbits->sidle_shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) goto set_midle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) best_mode = SYSC_IDLE_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) best_mode = fls(ddata->cfg.sidlemodes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (best_mode > SYSC_IDLE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dev_err(dev, "%s: invalid sidlemode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Set WAKEUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (regbits->enwkup_shift >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) reg |= BIT(regbits->enwkup_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) reg |= best_mode << regbits->sidle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) sysc_write_sysconfig(ddata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) set_midle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Set MIDLE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) idlemodes = ddata->cfg.midlemodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!idlemodes || regbits->midle_shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) goto set_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) best_mode = fls(ddata->cfg.midlemodes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (best_mode > SYSC_IDLE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dev_err(dev, "%s: invalid midlemode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) best_mode = SYSC_IDLE_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) reg |= best_mode << regbits->midle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) sysc_write_sysconfig(ddata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) set_autoidle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Autoidle bit must enabled separately if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (regbits->autoidle_shift >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) reg |= 1 << regbits->autoidle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) sysc_write_sysconfig(ddata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ddata->module_enable_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ddata->module_enable_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *best_mode = SYSC_IDLE_SMART_WKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else if (idlemodes & BIT(SYSC_IDLE_SMART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *best_mode = SYSC_IDLE_SMART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) else if (idlemodes & BIT(SYSC_IDLE_FORCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *best_mode = SYSC_IDLE_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int sysc_disable_module(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) const struct sysc_regbits *regbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u32 reg, idlemodes, best_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ddata->module_disable_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ddata->module_disable_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) regbits = ddata->cap->regbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Set MIDLE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) idlemodes = ddata->cfg.midlemodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!idlemodes || regbits->midle_shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) goto set_sidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = sysc_best_idle_mode(idlemodes, &best_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(dev, "%s: invalid midlemode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) best_mode = SYSC_IDLE_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) reg |= best_mode << regbits->midle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) sysc_write_sysconfig(ddata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) set_sidle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Set SIDLE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) idlemodes = ddata->cfg.sidlemodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (!idlemodes || regbits->sidle_shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) best_mode = SYSC_IDLE_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = sysc_best_idle_mode(idlemodes, &best_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dev_err(dev, "%s: invalid sidlemode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) reg |= best_mode << regbits->sidle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (regbits->autoidle_shift >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) reg |= 1 << regbits->autoidle_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) sysc_write_sysconfig(ddata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct ti_sysc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (!pdata->idle_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) error = pdata->idle_module(dev, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(dev, "%s: could not idle: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) reset_control_assert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct ti_sysc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!pdata->enable_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) error = pdata->enable_module(dev, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_err(dev, "%s: could not enable: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) reset_control_deassert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int __maybe_unused sysc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!ddata->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) sysc_clkdm_deny_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ddata->legacy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) error = sysc_runtime_suspend_legacy(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto err_allow_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) error = sysc_disable_module(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto err_allow_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sysc_disable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (sysc_opt_clks_needed(ddata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ddata->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) err_allow_idle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) reset_control_assert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int __maybe_unused sysc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ddata->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) sysc_clkdm_deny_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (sysc_opt_clks_needed(ddata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) error = sysc_enable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto err_allow_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) error = sysc_enable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto err_opt_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) reset_control_deassert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (ddata->legacy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) error = sysc_runtime_resume_legacy(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) goto err_main_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) error = sysc_enable_module(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) goto err_main_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ddata->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) err_main_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) sysc_disable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) err_opt_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (sysc_opt_clks_needed(ddata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) err_allow_idle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct device *dev = ddata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Disable target module if it is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (ddata->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) error = sysc_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_warn(dev, "reinit suspend failed: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* Enable target module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) error = sysc_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev_warn(dev, "reinit resume failed: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (leave_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* Disable target module if no leave_enabled was set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) error = sysc_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_warn(dev, "reinit suspend failed: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int __maybe_unused sysc_noirq_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ddata->cfg.quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (!ddata->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ddata->needs_resume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return sysc_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static int __maybe_unused sysc_noirq_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (ddata->cfg.quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) error = sysc_reinit_module(ddata, ddata->needs_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) dev_warn(dev, "noirq_resume failed: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) } else if (ddata->needs_resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) error = sysc_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_warn(dev, "noirq_resume failed: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ddata->needs_resume = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const struct dev_pm_ops sysc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) sysc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Module revision register based quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct sysc_revision_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int rev_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int sysc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int syss_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u32 revision_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) optrev_val, optrevmask, optquirkmask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .name = (optname), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .base = (optbase), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .rev_offset = (optrev), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .sysc_offset = (optsysc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .syss_offset = (optsyss), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .revision = (optrev_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .revision_mask = (optrevmask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .quirks = (optquirkmask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static const struct sysc_revision_quirk sysc_revision_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* Uarts on omap4 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Quirks that need to be set based on the module address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) SYSC_QUIRK_SWSUP_SIDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* Quirks that need to be set based on detected module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SYSC_MODULE_QUIRK_AESS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* Errata i893 handling for dra7 dcan1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) SYSC_QUIRK_CLKDM_NOAUTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) SYSC_QUIRK_CLKDM_NOAUTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) SYSC_QUIRK_CLKDM_NOAUTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) SYSC_QUIRK_CLKDM_NOAUTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SYSC_QUIRK_GPMC_DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) SYSC_QUIRK_OPT_CLKS_NEEDED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) SYSC_MODULE_QUIRK_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SYSC_MODULE_QUIRK_RTC_UNLOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) SYSC_QUIRK_REINIT_ON_CTX_LOST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) SYSC_MODULE_QUIRK_WDT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* PRUSS on am3, am4 and am5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) SYSC_MODULE_QUIRK_PRUSS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* Watchdog on am3 and am4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) 0xffff00f0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* Some timers on omap4 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * Early quirks based on module base and register offsets only that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * needed before the module revision can be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static void sysc_init_early_quirks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) const struct sysc_revision_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) q = &sysc_revision_quirks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (!q->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (q->base != ddata->module_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (q->rev_offset != ddata->offsets[SYSC_REVISION])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ddata->name = q->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ddata->cfg.quirks |= q->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* Quirks that also consider the revision register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static void sysc_init_revision_quirks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) const struct sysc_revision_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) q = &sysc_revision_quirks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (q->base && q->base != ddata->module_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (q->rev_offset != ddata->offsets[SYSC_REVISION])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (q->revision == ddata->revision ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) (q->revision & q->revision_mask) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) (ddata->revision & q->revision_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ddata->name = q->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ddata->cfg.quirks |= q->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * DSS needs dispc outputs disabled to reset modules. Returns mask of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * enabled DSS interrupts. Eventually we may be able to do this on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * dispc init rather than top-level DSS init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) bool disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) int manager_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) bool framedonetv_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) u32 val, irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) switch (sysc_soc->soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) case SOC_2420 ... SOC_3630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) manager_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) framedonetv_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) case SOC_4430 ... SOC_4470:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) manager_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) case SOC_5430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case SOC_DRA7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) manager_count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) case SOC_AM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) manager_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) framedonetv_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) case SOC_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* Remap the whole module range to be able to reset dispc outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) devm_iounmap(ddata->dev, ddata->module_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ddata->module_va = devm_ioremap(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ddata->module_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ddata->module_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (!ddata->module_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* DISP_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) val = sysc_read(ddata, dispc_offset + 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) lcd_en = val & lcd_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) digit_en = val & digit_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (lcd_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) irq_mask |= BIT(0); /* FRAMEDONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (digit_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (framedonetv_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) irq_mask |= BIT(24); /* FRAMEDONETV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (disable & (lcd_en | digit_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) sysc_write(ddata, dispc_offset + 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) val & ~(lcd_en_mask | digit_en_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (manager_count <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* DISPC_CONTROL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) val = sysc_read(ddata, dispc_offset + 0x238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) lcd2_en = val & lcd_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (lcd2_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) irq_mask |= BIT(22); /* FRAMEDONE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (disable && lcd2_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) sysc_write(ddata, dispc_offset + 0x238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) val & ~lcd_en_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (manager_count <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* DISPC_CONTROL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) val = sysc_read(ddata, dispc_offset + 0x848);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) lcd3_en = val & lcd_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (lcd3_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) irq_mask |= BIT(30); /* FRAMEDONE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (disable && lcd3_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) sysc_write(ddata, dispc_offset + 0x848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) val & ~lcd_en_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* DSS needs child outputs disabled and SDI registers cleared for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) const int dispc_offset = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) u32 irq_mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* Get enabled outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (!irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* Clear IRQSTATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) sysc_write(ddata, dispc_offset + 0x18, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /* Disable outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) val = sysc_quirk_dispc(ddata, dispc_offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Poll IRQSTATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) val, val != irq_mask, 100, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) __func__, val, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (sysc_soc->soc == SOC_3430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* Clear DSS_SDI_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) sysc_write(ddata, 0x44, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* Clear DSS_PLL_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) sysc_write(ddata, 0x48, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) sysc_write(ddata, 0x40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* 1-wire needs module's internal clocks enabled for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int offset = 0x0c; /* HDQ_CTRL_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) val = sysc_read(ddata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) val |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) sysc_write(ddata, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* AESS (Audio Engine SubSystem) needs autogating set after enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static void sysc_module_enable_quirk_aess(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) sysc_write(ddata, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* I2C needs to be disabled for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* I2C_CON, omap2/3 is different from omap4 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if ((ddata->revision & 0xffffff00) == 0x001f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) offset = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) offset = 0xa4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* I2C_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) val = sysc_read(ddata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) val |= BIT(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) val &= ~BIT(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) sysc_write(ddata, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) sysc_clk_quirk_i2c(ddata, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) sysc_clk_quirk_i2c(ddata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) u32 val, kick0_val = 0, kick1_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (!lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) kick0_val = 0x83e70b13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) kick1_val = 0x95a4f1e0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) !(val & BIT(0)), 100, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) dev_warn(ddata->dev, "rtc busy timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* Now we have ~15 microseconds to read/write various registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) sysc_write(ddata, 0x6c, kick0_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) sysc_write(ddata, 0x70, kick1_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) sysc_quirk_rtc(ddata, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) sysc_quirk_rtc(ddata, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int offset = 0xff08; /* OCP_DEBUG_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) u32 val = BIT(31); /* THALIA_INT_BYPASS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) sysc_write(ddata, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /* Watchdog timer needs a disable sequence after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) int wps, spr, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) wps = 0x34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) spr = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) sysc_write(ddata, spr, 0xaaaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) error = readl_poll_timeout(ddata->module_va + wps, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) !(val & 0x10), 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dev_warn(ddata->dev, "wdt disable step1 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) sysc_write(ddata, spr, 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) error = readl_poll_timeout(ddata->module_va + wps, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) !(val & 0x10), 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_warn(ddata->dev, "wdt disable step2 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) reg |= SYSC_PRUSS_STANDBY_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static void sysc_init_module_quirks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (ddata->legacy_mode || !ddata->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #ifdef CONFIG_OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static int sysc_clockdomain_init(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct clk *fck = NULL, *ick = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (!pdata || !pdata->init_clockdomain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) switch (ddata->nr_clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ick = ddata->clocks[SYSC_ICK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) fck = ddata->clocks[SYSC_FCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (!error || error == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * Note that pdata->init_module() typically does a reset first. After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * pdata->init_module() is done, PM runtime can be used for the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * target module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static int sysc_legacy_init(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (!pdata || !pdata->init_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (error == -EEXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) * Note that the caller must ensure the interconnect target module is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) * before calling reset. Otherwise reset will not complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static int sysc_reset(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) int sysc_offset, sysc_val, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) u32 sysc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (ddata->legacy_mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ddata->cap->regbits->srst_shift < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) sysc_mask = BIT(ddata->cap->regbits->srst_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (ddata->pre_reset_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ddata->pre_reset_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (sysc_offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) sysc_val = sysc_read_sysconfig(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) sysc_val |= sysc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) sysc_write(ddata, sysc_offset, sysc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (ddata->cfg.srst_udelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) usleep_range(ddata->cfg.srst_udelay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ddata->cfg.srst_udelay * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (ddata->post_reset_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ddata->post_reset_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) error = sysc_wait_softreset(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) dev_warn(ddata->dev, "OCP softreset timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (ddata->reset_done_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ddata->reset_done_quirk(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) * At this point the module is configured enough to read the revision but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) * module may not be completely configured yet to use PM runtime. Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * all clocks directly during init to configure the quirks needed for PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) * runtime based on the revision register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static int sysc_init_module(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) error = sysc_clockdomain_init(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) sysc_clkdm_deny_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * Always enable clocks. The bootloader may or may not have enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * the related clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) error = sysc_enable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) error = sysc_enable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) goto err_opt_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) error = reset_control_deassert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) goto err_main_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ddata->revision = sysc_read_revision(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) sysc_init_revision_quirks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) sysc_init_module_quirks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (ddata->legacy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) error = sysc_legacy_init(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) goto err_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (!ddata->legacy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) error = sysc_enable_module(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) goto err_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) error = sysc_reset(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_err(ddata->dev, "Reset failed with %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (error && !ddata->legacy_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) sysc_disable_module(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) err_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) reset_control_assert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) err_main_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) sysc_disable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) err_opt_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* No re-enable of clockdomain autoidle to prevent module autoidle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static int sysc_init_sysc_mask(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) error = of_property_read_u32(np, "ti,sysc-mask", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) of_property_for_each_u32(np, name, prop, p, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (val >= SYSC_NR_IDLEMODES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) dev_err(ddata->dev, "invalid idlemode: %i\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) *idlemodes |= (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static int sysc_init_idlemodes(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) "ti,sysc-midle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) "ti,sysc-sidle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * Only some devices on omap4 and later have SYSCONFIG reset done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * bit. We can detect this if there is no SYSSTATUS at all, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * have multiple bits for the child devices like OHCI and EHCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * Depends on SYSC being parsed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static int sysc_init_syss_mask(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) error = of_property_read_u32(np, "ti,syss-mask", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if ((ddata->cap->type == TI_SYSC_OMAP4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ddata->cfg.syss_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) * Many child device drivers need to have fck and opt clocks available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) * to get the clock rate for device internal configuration etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static int sysc_child_add_named_clock(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct device *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct clk_lookup *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) clk = clk_get(child, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) error = -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) goto put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) clk = clk_get(ddata->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) l = clkdev_create(clk, name, dev_name(child));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) static int sysc_child_add_clocks(struct sysc *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct device *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) int i, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) for (i = 0; i < ddata->nr_clocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) error = sysc_child_add_named_clock(ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ddata->clock_roles[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (error && error != -EEXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_err(ddata->dev, "could not add child clock %s: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ddata->clock_roles[i], error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static struct device_type sysc_device_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static struct sysc *sysc_child_to_parent(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct device *parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (!parent || parent->type != &sysc_device_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return dev_get_drvdata(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ddata = sysc_child_to_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) error = pm_generic_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (!ddata->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) return sysc_runtime_suspend(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ddata = sysc_child_to_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (!ddata->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) error = sysc_runtime_resume(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) dev_err(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) "%s error: %i\n", __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return pm_generic_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static int sysc_child_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ddata = sysc_child_to_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) dev_dbg(ddata->dev, "%s %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ddata->name ? ddata->name : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) error = pm_generic_suspend_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) dev_err(dev, "%s error at %i: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) __func__, __LINE__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) if (!pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) error = pm_generic_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) dev_dbg(dev, "%s busy at %i: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) __func__, __LINE__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) error = sysc_runtime_suspend(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) dev_err(dev, "%s error at %i: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) __func__, __LINE__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ddata->child_needs_resume = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) static int sysc_child_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) ddata = sysc_child_to_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) dev_dbg(ddata->dev, "%s %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ddata->name ? ddata->name : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (ddata->child_needs_resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ddata->child_needs_resume = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) error = sysc_runtime_resume(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) dev_err(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) "%s runtime resume error: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) error = pm_generic_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) dev_err(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) "%s generic runtime resume: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) return pm_generic_resume_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static struct dev_pm_domain sysc_child_pm_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) sysc_child_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) USE_PLATFORM_PM_SLEEP_OPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) sysc_child_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* Caller needs to take list_lock if ever used outside of cpu_pm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static void sysc_reinit_modules(struct sysc_soc_info *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) struct sysc_module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) list_for_each(pos, &sysc_soc->restored_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) module = list_entry(pos, struct sysc_module, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ddata = module->ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) sysc_reinit_module(ddata, ddata->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) * sysc_context_notifier - optionally reset and restore module after idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * @nb: notifier block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) * @cmd: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) * @v: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * Some interconnect target modules need to be restored, or reset and restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * OTG and GPMC target modules even if the modules are unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) struct sysc_soc_info *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) soc = container_of(nb, struct sysc_soc_info, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) sysc_reinit_modules(soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * sysc_add_restored - optionally add reset and restore quirk hanlling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) * @ddata: device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static void sysc_add_restored(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) struct sysc_module *restored_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (!restored_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) restored_module->ddata = ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) mutex_lock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) list_add(&restored_module->node, &sysc_soc->restored_modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (sysc_soc->nb.notifier_call)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) sysc_soc->nb.notifier_call = sysc_context_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) cpu_pm_register_notifier(&sysc_soc->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) mutex_unlock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) * sysc_legacy_idle_quirk - handle children in omap_device compatible way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) * @ddata: device driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) * @child: child device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) * Allow idle for child devices as done with _od_runtime_suspend().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) * Otherwise many child devices will not idle because of the permanent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) * parent usecount set in pm_runtime_irq_safe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * Note that the long term solution is to just modify the child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) * drivers to not set pm_runtime_irq_safe() and then this can be just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) * dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) dev_pm_domain_set(child, &sysc_child_pm_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) static int sysc_notifier_call(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) unsigned long event, void *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) struct device *dev = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ddata = sysc_child_to_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) case BUS_NOTIFY_ADD_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) error = sysc_child_add_clocks(ddata, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) sysc_legacy_idle_quirk(ddata, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) static struct notifier_block sysc_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .notifier_call = sysc_notifier_call,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* Device tree configured quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) struct sysc_dts_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static const struct sysc_dts_quirk sysc_dts_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) { .name = "ti,no-idle-on-init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { .name = "ti,no-reset-on-init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) { .name = "ti,no-idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .mask = SYSC_QUIRK_NO_IDLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) bool is_child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) const struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) const char *name = sysc_dts_quirks[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) prop = of_get_property(np, name, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (is_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) dev_warn(ddata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) "dts flag should be at module level for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static int sysc_init_dts_quirks(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) struct device_node *np = ddata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) sysc_parse_dts_quirks(ddata, np, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (!error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (val > 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ddata->cfg.srst_udelay = (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static void sysc_unprepare(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (!ddata->clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (!IS_ERR_OR_NULL(ddata->clocks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) clk_unprepare(ddata->clocks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) * Common sysc register bits found on omap2, also known as type1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) static const struct sysc_regbits sysc_regbits_omap2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .midle_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .sidle_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .clkact_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .emufree_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .enwkup_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .srst_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .autoidle_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) static const struct sysc_capabilities sysc_omap2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .type = TI_SYSC_OMAP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) SYSC_OMAP2_AUTOIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .regbits = &sysc_regbits_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static const struct sysc_capabilities sysc_omap2_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .type = TI_SYSC_OMAP2_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) SYSC_OMAP2_AUTOIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) .regbits = &sysc_regbits_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) * with different sidle position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static const struct sysc_regbits sysc_regbits_omap3_sham = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .sidle_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .srst_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .autoidle_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) static const struct sysc_capabilities sysc_omap3_sham = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .type = TI_SYSC_OMAP3_SHAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .regbits = &sysc_regbits_omap3_sham,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) * AES register bits found on omap3 and later, a variant of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) * sysc_regbits_omap2 with different sidle position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) static const struct sysc_regbits sysc_regbits_omap3_aes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .sidle_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .srst_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .autoidle_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static const struct sysc_capabilities sysc_omap3_aes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .type = TI_SYSC_OMAP3_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .regbits = &sysc_regbits_omap3_aes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * Common sysc register bits found on omap4, also known as type2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static const struct sysc_regbits sysc_regbits_omap4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .dmadisable_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .midle_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .sidle_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .emufree_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .srst_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static const struct sysc_capabilities sysc_omap4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .type = TI_SYSC_OMAP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) SYSC_OMAP4_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .regbits = &sysc_regbits_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static const struct sysc_capabilities sysc_omap4_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .type = TI_SYSC_OMAP4_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) SYSC_OMAP4_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .regbits = &sysc_regbits_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * Common sysc register bits found on omap4, also known as type3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static const struct sysc_regbits sysc_regbits_omap4_simple = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .midle_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .sidle_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .srst_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) static const struct sysc_capabilities sysc_omap4_simple = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .type = TI_SYSC_OMAP4_SIMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .regbits = &sysc_regbits_omap4_simple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) * SmartReflex sysc found on omap34xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .sidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .clkact_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .srst_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static const struct sysc_capabilities sysc_34xx_sr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .type = TI_SYSC_OMAP34XX_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .regbits = &sysc_regbits_omap34xx_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) SYSC_QUIRK_LEGACY_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) * SmartReflex sysc found on omap36xx and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .sidle_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .enwkup_shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .srst_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) static const struct sysc_capabilities sysc_36xx_sr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .type = TI_SYSC_OMAP36XX_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .regbits = &sysc_regbits_omap36xx_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static const struct sysc_capabilities sysc_omap4_sr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .type = TI_SYSC_OMAP4_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .regbits = &sysc_regbits_omap36xx_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) * McASP register bits found on omap4 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .sidle_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .enwkup_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) .srst_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static const struct sysc_capabilities sysc_omap4_mcasp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .type = TI_SYSC_OMAP4_MCASP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .regbits = &sysc_regbits_omap4_mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) * McASP found on dra7 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) static const struct sysc_capabilities sysc_dra7_mcasp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .type = TI_SYSC_OMAP4_SIMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .regbits = &sysc_regbits_omap4_simple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) * FS USB host found on omap4 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .sidle_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .enwkup_shift = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .srst_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .type = TI_SYSC_OMAP4_USB_HOST_FS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .regbits = &sysc_regbits_omap4_usb_host_fs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) static const struct sysc_regbits sysc_regbits_dra7_mcan = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .dmadisable_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .midle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .sidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .clkact_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .enwkup_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .srst_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .emufree_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .autoidle_shift = -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static const struct sysc_capabilities sysc_dra7_mcan = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .type = TI_SYSC_DRA7_MCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .regbits = &sysc_regbits_dra7_mcan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) static const struct sysc_capabilities sysc_pruss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .type = TI_SYSC_PRUSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .regbits = &sysc_regbits_omap4_simple,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static int sysc_init_pdata(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) struct ti_sysc_module_data *mdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) if (!mdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (ddata->legacy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) mdata->name = ddata->legacy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) mdata->module_pa = ddata->module_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) mdata->module_size = ddata->module_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) mdata->offsets = ddata->offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) mdata->nr_offsets = SYSC_MAX_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) mdata->cap = ddata->cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) mdata->cfg = &ddata->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) ddata->mdata = mdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static int sysc_init_match(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) const struct sysc_capabilities *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) cap = of_device_get_match_data(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ddata->cap = cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) if (ddata->cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) ddata->cfg.quirks |= ddata->cap->mod_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) static void ti_sysc_idle(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) ddata = container_of(work, struct sysc, idle_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) * One time decrement of clock usage counts if left on from init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) * Note that we disable opt clocks unconditionally in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) * as they are enabled unconditionally during init without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) * considering sysc_opt_clks_needed() at that point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) SYSC_QUIRK_NO_IDLE_ON_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) sysc_disable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) * and SYSC_QUIRK_NO_RESET_ON_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (pm_runtime_active(ddata->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) pm_runtime_put_sync(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * SoC model and features detection. Only needed for SoCs that need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * special handling for quirks, no need to list others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static const struct soc_device_attribute sysc_soc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) SOC_FLAG("OMAP242*", SOC_2420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) SOC_FLAG("OMAP243*", SOC_2430),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) SOC_FLAG("OMAP3[45]*", SOC_3430),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) SOC_FLAG("OMAP3[67]*", SOC_3630),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) SOC_FLAG("OMAP443*", SOC_4430),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) SOC_FLAG("OMAP446*", SOC_4460),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) SOC_FLAG("OMAP447*", SOC_4470),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) SOC_FLAG("OMAP54*", SOC_5430),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) SOC_FLAG("AM433", SOC_AM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) SOC_FLAG("AM43*", SOC_AM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) SOC_FLAG("DRA7*", SOC_DRA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) * List of SoCs variants with disabled features. By default we assume all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) * devices in the device tree are available so no need to list those SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) static const struct soc_device_attribute sysc_soc_feat_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) SOC_FLAG("AM3505", DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) SOC_FLAG("OMAP3525", DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* OMAP3630/DM3730 variants with some accelerators disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) SOC_FLAG("DM3725", DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) SOC_FLAG("OMAP3621", DIS_ISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static int sysc_add_disabled(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) struct sysc_address *disabled_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (!disabled_module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) disabled_module->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) mutex_lock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) list_add(&disabled_module->node, &sysc_soc->disabled_modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) mutex_unlock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) * One time init to detect the booted SoC, disable unavailable features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * and initialize list for optional cpu_pm notifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) * Note that we initialize static data shared across all ti-sysc instances
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * so ddata is only used for SoC type. This can be called from module_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) * once we no longer need to rely on platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static int sysc_init_static_data(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) const struct soc_device_attribute *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) struct ti_sysc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) unsigned long features = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) if (sysc_soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) if (!sysc_soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) mutex_init(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) INIT_LIST_HEAD(&sysc_soc->disabled_modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) INIT_LIST_HEAD(&sysc_soc->restored_modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) sysc_soc->general_purpose = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) pdata = dev_get_platdata(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (pdata && pdata->soc_type_gp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) sysc_soc->general_purpose = pdata->soc_type_gp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) match = soc_device_match(sysc_soc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) if (match && match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) sysc_soc->soc = (int)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) /* Ignore devices that are not available on HS and EMU SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if (!sysc_soc->general_purpose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) switch (sysc_soc->soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) case SOC_3430 ... SOC_3630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) sysc_add_disabled(0x48304000); /* timer12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) case SOC_AM3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) sysc_add_disabled(0x48310000); /* rng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) match = soc_device_match(sysc_soc_feat_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) if (match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) features = (unsigned long)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) * Add disabled devices to the list based on the module base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) * Note that this must be done before we attempt to access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) * device and have module revision checks working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) if (features & DIS_ISP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) sysc_add_disabled(0x480bd400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) if (features & DIS_IVA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) sysc_add_disabled(0x5d000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) if (features & DIS_SGX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) sysc_add_disabled(0x50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static void sysc_cleanup_static_data(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) struct sysc_module *restored_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) struct sysc_address *disabled_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) struct list_head *pos, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) if (!sysc_soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (sysc_soc->nb.notifier_call)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) cpu_pm_unregister_notifier(&sysc_soc->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) mutex_lock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) restored_module = list_entry(pos, struct sysc_module, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) list_del(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) kfree(restored_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) disabled_module = list_entry(pos, struct sysc_address, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) list_del(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) kfree(disabled_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) mutex_unlock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) static int sysc_check_disabled_devices(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) struct sysc_address *disabled_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) mutex_lock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) list_for_each(pos, &sysc_soc->disabled_modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) disabled_module = list_entry(pos, struct sysc_address, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) if (ddata->module_pa == disabled_module->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) dev_dbg(ddata->dev, "module disabled for this SoC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) error = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) mutex_unlock(&sysc_soc->list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) * Ignore timers tagged with no-reset and no-idle. These are likely in use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) * are needed, we could also look at the timer register configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) static int sysc_check_active_timer(struct sysc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) ddata->cap->type != TI_SYSC_OMAP4_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) static const struct of_device_id sysc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) { .compatible = "simple-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) static int sysc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) struct sysc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) ddata->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) platform_set_drvdata(pdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) error = sysc_init_static_data(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) error = sysc_init_match(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) error = sysc_init_dts_quirks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) error = sysc_map_and_check_registers(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) error = sysc_init_sysc_mask(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) error = sysc_init_idlemodes(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) error = sysc_init_syss_mask(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) error = sysc_init_pdata(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) sysc_init_early_quirks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) error = sysc_check_disabled_devices(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) error = sysc_check_active_timer(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (error == -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) ddata->reserved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) else if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) error = sysc_get_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) error = sysc_init_resets(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) goto unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) error = sysc_init_module(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) goto unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) pm_runtime_enable(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) error = pm_runtime_get_sync(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) pm_runtime_put_noidle(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) pm_runtime_disable(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) goto unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) /* Balance use counts as PM runtime should have enabled these all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) reset_control_assert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (!(ddata->cfg.quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) sysc_disable_main_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) sysc_disable_opt_clocks(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) sysc_clkdm_allow_idle(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) sysc_show_registers(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) ddata->dev->type = &sysc_device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) if (!ddata->reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) error = of_platform_populate(ddata->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) sysc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) pdata ? pdata->auxdata : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) /* At least earlycon won't survive without deferred idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) SYSC_QUIRK_NO_IDLE_ON_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) SYSC_QUIRK_NO_RESET_ON_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) schedule_delayed_work(&ddata->idle_work, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) sysc_add_restored(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) sysc_unprepare(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) static int sysc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) struct sysc *ddata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) cancel_delayed_work_sync(&ddata->idle_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) error = pm_runtime_get_sync(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) pm_runtime_put_noidle(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) pm_runtime_disable(ddata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) goto unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) if (!reset_control_status(ddata->rsts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) reset_control_assert(ddata->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) sysc_unprepare(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) static const struct of_device_id sysc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) { .compatible = "ti,sysc-usb-host-fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) .data = &sysc_omap4_usb_host_fs, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) MODULE_DEVICE_TABLE(of, sysc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) static struct platform_driver sysc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .probe = sysc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .remove = sysc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) .name = "ti-sysc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) .of_match_table = sysc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) .pm = &sysc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static int __init sysc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) bus_register_notifier(&platform_bus_type, &sysc_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) return platform_driver_register(&sysc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) module_init(sysc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) static void __exit sysc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) bus_unregister_notifier(&platform_bus_type, &sysc_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) platform_driver_unregister(&sysc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) sysc_cleanup_static_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) module_exit(sysc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) MODULE_DESCRIPTION("TI sysc interconnect target driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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