^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for NVIDIA Generic Memory Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Host Mobility AB. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA_GMI_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_GMI_CONFIG_GO BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA_GMI_MUX_MODE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_GMI_TIMING0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_GMI_TIMING1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_GMI_MAX_CHIP_SELECT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct tegra_gmi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 snor_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 snor_timing0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 snor_timing1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int tegra_gmi_enable(struct tegra_gmi *gmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) err = clk_prepare_enable(gmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_err(gmi->dev, "failed to enable clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reset_control_assert(gmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) reset_control_deassert(gmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void tegra_gmi_disable(struct tegra_gmi *gmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* stop GMI operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) config = readl(gmi->base + TEGRA_GMI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) config &= ~TEGRA_GMI_CONFIG_GO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(config, gmi->base + TEGRA_GMI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reset_control_assert(gmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk_disable_unprepare(gmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 property, ranges[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) child = of_get_next_available_child(gmi->dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(gmi->dev, "no child nodes found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * We currently only support one child device due to lack of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * chip-select address decoding. Which means that we only have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * chip-select line from the GMI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (of_get_child_count(gmi->dev->of_node) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_warn(gmi->dev, "only one child device is supported.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) gmi->snor_config |= TEGRA_GMI_MUX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Decode the CS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) err = of_property_read_u32_array(child, "ranges", ranges, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Invalid binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (err == -EOVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(gmi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "failed to decode CS: invalid ranges length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto error_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * If we reach here it means that the child node has an empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * ranges or it does not exist at all. Attempt to decode the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * CS# from the reg property instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) err = of_property_read_u32(child, "reg", &property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(gmi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "failed to decode CS: no reg property found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto error_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) property = ranges[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Valid chip selects are CS0-CS7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(gmi->dev, "invalid chip select: %d", property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto error_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* The default values that are provided below are reset values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) error_cs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int tegra_gmi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct tegra_gmi *gmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!gmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) gmi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gmi->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(gmi->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PTR_ERR(gmi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) gmi->clk = devm_clk_get(dev, "gmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(gmi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(dev, "can not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR(gmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) gmi->rst = devm_reset_control_get(dev, "gmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(gmi->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dev, "can not get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(gmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) err = tegra_gmi_parse_dt(gmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = tegra_gmi_enable(gmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = of_platform_default_populate(dev->of_node, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "fail to create devices.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tegra_gmi_disable(gmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) platform_set_drvdata(pdev, gmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int tegra_gmi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tegra_gmi *gmi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) of_platform_depopulate(gmi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tegra_gmi_disable(gmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id tegra_gmi_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .compatible = "nvidia,tegra20-gmi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .compatible = "nvidia,tegra30-gmi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct platform_driver tegra_gmi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .probe = tegra_gmi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .remove = tegra_gmi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "tegra-gmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .of_match_table = tegra_gmi_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(tegra_gmi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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