Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Tegra ACONNECT Bus Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) struct tegra_aconnect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	struct clk	*ape_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct clk	*apb2ape_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int tegra_aconnect_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct tegra_aconnect *aconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	aconnect = devm_kzalloc(&pdev->dev, sizeof(struct tegra_aconnect),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (!aconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	aconnect->ape_clk = devm_clk_get(&pdev->dev, "ape");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (IS_ERR(aconnect->ape_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		dev_err(&pdev->dev, "Can't retrieve ape clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return PTR_ERR(aconnect->ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	aconnect->apb2ape_clk = devm_clk_get(&pdev->dev, "apb2ape");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (IS_ERR(aconnect->apb2ape_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		dev_err(&pdev->dev, "Can't retrieve apb2ape clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		return PTR_ERR(aconnect->apb2ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	dev_set_drvdata(&pdev->dev, aconnect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	dev_info(&pdev->dev, "Tegra ACONNECT bus registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int tegra_aconnect_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int tegra_aconnect_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct tegra_aconnect *aconnect = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	ret = clk_prepare_enable(aconnect->ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		dev_err(dev, "ape clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret = clk_prepare_enable(aconnect->apb2ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		clk_disable_unprepare(aconnect->ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		dev_err(dev, "apb2ape clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int tegra_aconnect_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct tegra_aconnect *aconnect = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	clk_disable_unprepare(aconnect->ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	clk_disable_unprepare(aconnect->apb2ape_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static const struct dev_pm_ops tegra_aconnect_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	SET_RUNTIME_PM_OPS(tegra_aconnect_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			   tegra_aconnect_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				      pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct of_device_id tegra_aconnect_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ .compatible = "nvidia,tegra210-aconnect", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_DEVICE_TABLE(of, tegra_aconnect_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct platform_driver tegra_aconnect_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.probe = tegra_aconnect_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.remove = tegra_aconnect_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.name = "tegra-aconnect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.of_match_table = tegra_aconnect_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.pm = &tegra_aconnect_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) module_platform_driver(tegra_aconnect_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_DESCRIPTION("NVIDIA Tegra ACONNECT Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_LICENSE("GPL v2");