^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * RSB (Reduced Serial Bus) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The RSB controller looks like an SMBus controller which only supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * byte and word data transfers. But, it differs from standard SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * protocol on several aspects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - it uses addresses set at runtime to address slaves. Runtime addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * are sent to slaves using their 12bit hardware addresses. Up to 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * runtime addresses are available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - it adds a parity bit every 8bits of data and address for read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * write accesses; this replaces the ack bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - only one read access is required to read a byte (instead of a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * followed by a read access in standard SMBus protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - there's no Ack bit after each read access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This means this bus cannot be used to interface with standard SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * devices. Devices known to support this interface include the AXP223,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * A description of the operation and wire protocol can be found in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * RSB section of Allwinner's A80 user manual, which can be found at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * https://github.com/allwinner-zh/documents/tree/master/A80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * This document is officially released by Allwinner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/clk/clk-conf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/sunxi-rsb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* RSB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RSB_CTRL 0x0 /* Global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RSB_CCR 0x4 /* Clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RSB_INTE 0x8 /* Interrupt controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RSB_INTS 0xc /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RSB_ADDR 0x10 /* Address to send with read/write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RSB_DATA 0x1c /* Data to read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RSB_LCR 0x24 /* Line control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RSB_DMCR 0x28 /* Device mode (init) control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RSB_CMD 0x2c /* RSB Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RSB_DAR 0x30 /* Device address / runtime address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RSB_CTRL_START_TRANS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RSB_CTRL_ABORT_TRANS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RSB_CTRL_GLOBAL_INT_ENB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RSB_CTRL_SOFT_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CLK CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RSB_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RSB_CCR_MAX_CLK_DIV 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RSB_CCR_CLK_DIV(v) ((v) & RSB_CCR_MAX_CLK_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* STATUS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RSB_INTS_TRANS_ERR_ACK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) >> 8) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RSB_INTS_TRANS_ERR_DATA GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RSB_INTS_LOAD_BSY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RSB_INTS_TRANS_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RSB_INTS_TRANS_OVER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* LINE CTRL fields*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RSB_LCR_SCL_STATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RSB_LCR_SDA_STATE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RSB_LCR_SCL_CTL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RSB_LCR_SCL_CTL_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RSB_LCR_SDA_CTL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RSB_LCR_SDA_CTL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* DEVICE MODE CTRL field values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RSB_DMCR_DEVICE_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RSB_DMCR_MODE_DATA (0x7c << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RSB_DMCR_MODE_REG (0x3e << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RSB_DMCR_DEV_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* CMD values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RSB_CMD_RD8 0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RSB_CMD_RD16 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RSB_CMD_RD32 0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RSB_CMD_WR8 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RSB_CMD_WR16 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RSB_CMD_WR32 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RSB_CMD_STRA 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* DAR fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RSB_DAR_RTA(v) (((v) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RSB_DAR_DA(v) ((v) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RSB_MAX_FREQ 20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RSB_CTRL_NAME "sunxi-rsb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sunxi_rsb_addr_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 rtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sunxi_rsb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* bus / slave device related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct bus_type sunxi_rsb_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int sunxi_rsb_device_match(struct device *dev, struct device_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return of_driver_match_device(dev, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int sunxi_rsb_device_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!drv->probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!rdev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int irq = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) irq = of_irq_get(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rdev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = of_clk_set_defaults(dev->of_node, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return drv->probe(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int sunxi_rsb_device_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return drv->remove(to_sunxi_rsb_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct bus_type sunxi_rsb_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = RSB_CTRL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .match = sunxi_rsb_device_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .probe = sunxi_rsb_device_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .remove = sunxi_rsb_device_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .uevent = of_device_uevent_modalias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void sunxi_rsb_dev_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) kfree(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * sunxi_rsb_device_create() - allocate and add an RSB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @rsb: RSB controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @node: RSB slave device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @hwaddr: RSB slave hardware address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @rtaddr: RSB slave runtime address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct sunxi_rsb_device *sunxi_rsb_device_create(struct sunxi_rsb *rsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct device_node *node, u16 hwaddr, u8 rtaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sunxi_rsb_device *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rdev->rsb = rsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rdev->hwaddr = hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rdev->rtaddr = rtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rdev->dev.bus = &sunxi_rsb_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rdev->dev.parent = rsb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rdev->dev.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rdev->dev.release = sunxi_rsb_dev_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_set_name(&rdev->dev, "%s-%x", RSB_CTRL_NAME, hwaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) err = device_register(&rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(&rdev->dev, "Can't add %s, status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_name(&rdev->dev), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err_device_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) err_device_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) put_device(&rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * sunxi_rsb_device_unregister(): unregister an RSB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @rdev: rsb_device to be removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void sunxi_rsb_device_unregister(struct sunxi_rsb_device *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) device_unregister(&rdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sunxi_rsb_remove_devices(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (dev->bus == &sunxi_rsb_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sunxi_rsb_device_unregister(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * sunxi_rsb_driver_register() - Register device driver with RSB core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @rdrv: device driver to be associated with slave-device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * This API will register the client driver with the RSB framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * It is typically called from the driver's module-init function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int sunxi_rsb_driver_register(struct sunxi_rsb_driver *rdrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) rdrv->driver.bus = &sunxi_rsb_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return driver_register(&rdrv->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) EXPORT_SYMBOL_GPL(sunxi_rsb_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* common code that starts a transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (readl(rsb->regs + RSB_CTRL) & RSB_CTRL_START_TRANS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_dbg(rsb->dev, "RSB transfer still in progress\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reinit_completion(&rsb->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rsb->regs + RSB_INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rsb->regs + RSB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!wait_for_completion_io_timeout(&rsb->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msecs_to_jiffies(100))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(rsb->dev, "RSB timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* abort the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* clear any interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rsb->status & RSB_INTS_LOAD_BSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(rsb->dev, "RSB busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (rsb->status & RSB_INTS_TRANS_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (rsb->status & RSB_INTS_TRANS_ERR_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_dbg(rsb->dev, "RSB slave nack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (rsb->status & RSB_INTS_TRANS_ERR_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(rsb->dev, "RSB transfer data error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmd = RSB_CMD_RD8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cmd = RSB_CMD_RD16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cmd = RSB_CMD_RD32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(rsb->dev, "Invalid access width: %zd\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_lock(&rsb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(addr, rsb->regs + RSB_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(cmd, rsb->regs + RSB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = _sunxi_rsb_run_xfer(rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *buf = readl(rsb->regs + RSB_DATA) & GENMASK(len * 8 - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mutex_unlock(&rsb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int sunxi_rsb_write(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const u32 *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cmd = RSB_CMD_WR8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cmd = RSB_CMD_WR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cmd = RSB_CMD_WR32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(rsb->dev, "Invalid access width: %zd\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mutex_lock(&rsb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) writel(addr, rsb->regs + RSB_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(*buf, rsb->regs + RSB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(cmd, rsb->regs + RSB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = _sunxi_rsb_run_xfer(rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mutex_unlock(&rsb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* RSB regmap functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct sunxi_rsb_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct sunxi_rsb_device *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int regmap_sunxi_rsb_reg_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct sunxi_rsb_ctx *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct sunxi_rsb_device *rdev = ctx->rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct sunxi_rsb_ctx *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct sunxi_rsb_device *rdev = ctx->rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void regmap_sunxi_rsb_free_ctx(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sunxi_rsb_ctx *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct regmap_bus regmap_sunxi_rsb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .reg_write = regmap_sunxi_rsb_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .reg_read = regmap_sunxi_rsb_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .free_context = regmap_sunxi_rsb_free_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct sunxi_rsb_ctx *regmap_sunxi_rsb_init_ctx(struct sunxi_rsb_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const struct regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct sunxi_rsb_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (config->val_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ctx->rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ctx->size = config->val_bits / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct regmap *__devm_regmap_init_sunxi_rsb(struct sunxi_rsb_device *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) const struct regmap_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct lock_class_key *lock_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) const char *lock_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct sunxi_rsb_ctx *ctx = regmap_sunxi_rsb_init_ctx(rdev, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (IS_ERR(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ERR_CAST(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return __devm_regmap_init(&rdev->dev, ®map_sunxi_rsb, ctx, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) lock_key, lock_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) EXPORT_SYMBOL_GPL(__devm_regmap_init_sunxi_rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* RSB controller driver functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct sunxi_rsb *rsb = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) status = readl(rsb->regs + RSB_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) rsb->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RSB_INTS_TRANS_OVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(status, rsb->regs + RSB_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) complete(&rsb->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* send init sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) writel(RSB_DMCR_DEVICE_START | RSB_DMCR_MODE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) RSB_DMCR_MODE_REG | RSB_DMCR_DEV_ADDR, rsb->regs + RSB_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) readl_poll_timeout(rsb->regs + RSB_DMCR, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) !(reg & RSB_DMCR_DEVICE_START), 100, 250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (reg & RSB_DMCR_DEVICE_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* clear interrupt status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * There are 15 valid runtime addresses, though Allwinner typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * skips the first, for unknown reasons, and uses the following three.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * 0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * No designs with 2 RSB slave devices sharing identical hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * addresses on the same bus have been seen in the wild. All designs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * use 0x2d for the primary PMIC, 0x3a for the secondary PMIC if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * there is one, and 0x45 for peripheral ICs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * The hardware does not seem to support re-setting runtime addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Attempts to do so result in the slave devices returning a NACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Hence we just hardcode the mapping here, like Allwinner does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 0x3a3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { 0xe89, 0x4e }, /* Peripheral IC: AC100, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static u8 sunxi_rsb_get_rtaddr(u16 hwaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < ARRAY_SIZE(sunxi_rsb_addr_maps); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (hwaddr == sunxi_rsb_addr_maps[i].hwaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return sunxi_rsb_addr_maps[i].rtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0; /* 0 is an invalid runtime address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int of_rsb_register_devices(struct sunxi_rsb *rsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct device *dev = rsb->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct device_node *child, *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u8 rtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Runtime addresses for all slaves should be set first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_dbg(dev, "setting child %pOF runtime address\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = of_property_read_u32(child, "reg", &hwaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(dev, "%pOF: invalid 'reg' property: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) child, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!rtaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(dev, "%pOF: unknown hardware device address\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Since no devices have been registered yet, we are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * only ones using the bus, we can skip locking the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* setup command parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writel(RSB_CMD_STRA, rsb->regs + RSB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writel(RSB_DAR_RTA(rtaddr) | RSB_DAR_DA(hwaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rsb->regs + RSB_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* send command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = _sunxi_rsb_run_xfer(rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_warn(dev, "%pOF: set runtime address failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) child, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Then we start adding devices and probing them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct sunxi_rsb_device *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(dev, "adding child %pOF\n", child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = of_property_read_u32(child, "reg", &hwaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!rtaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rdev = sunxi_rsb_device_create(rsb, child, hwaddr, rtaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (IS_ERR(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "failed to add child device %pOF: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) child, PTR_ERR(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct of_device_id sunxi_rsb_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "allwinner,sun8i-a23-rsb" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int sunxi_rsb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct sunxi_rsb *rsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned long p_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 clk_delay, clk_freq = 3000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int clk_div, irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) of_property_read_u32(np, "clock-frequency", &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (clk_freq > RSB_MAX_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "clock-frequency (%u Hz) is too high (max = 20MHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rsb = devm_kzalloc(dev, sizeof(*rsb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!rsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rsb->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) platform_set_drvdata(pdev, rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) rsb->regs = devm_ioremap_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (IS_ERR(rsb->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return PTR_ERR(rsb->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rsb->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (IS_ERR(rsb->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = PTR_ERR(rsb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(dev, "failed to retrieve clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = clk_prepare_enable(rsb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_err(dev, "failed to enable clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) p_clk_freq = clk_get_rate(rsb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rsb->rstc = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (IS_ERR(rsb->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = PTR_ERR(rsb->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = reset_control_deassert(rsb->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(dev, "failed to deassert reset line: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) init_completion(&rsb->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mutex_init(&rsb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) readl_poll_timeout(rsb->regs + RSB_CTRL, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) !(reg & RSB_CTRL_SOFT_RST), 1000, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Clock frequency and delay calculation code is from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Allwinner U-boot sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * From A83 user manual:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * bus clock frequency = parent clock frequency / (2 * (divider + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) clk_div = p_clk_freq / clk_freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!clk_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) clk_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) clk_div = RSB_CCR_MAX_CLK_DIV + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) clk_delay = clk_div >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!clk_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) clk_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rsb->regs + RSB_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = devm_request_irq(dev, irq, sunxi_rsb_irq, 0, RSB_CTRL_NAME, rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(dev, "can't register interrupt handler irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto err_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* initialize all devices on the bus into RSB mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = sunxi_rsb_init_device_mode(rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_warn(dev, "Initialize device mode failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) of_rsb_register_devices(rsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err_reset_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) reset_control_assert(rsb->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk_disable_unprepare(rsb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int sunxi_rsb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct sunxi_rsb *rsb = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) reset_control_assert(rsb->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_disable_unprepare(rsb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct platform_driver sunxi_rsb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .probe = sunxi_rsb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .remove = sunxi_rsb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .name = RSB_CTRL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .of_match_table = sunxi_rsb_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int __init sunxi_rsb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = bus_register(&sunxi_rsb_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pr_err("failed to register sunxi sunxi_rsb bus: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return platform_driver_register(&sunxi_rsb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) module_init(sunxi_rsb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void __exit sunxi_rsb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) platform_driver_unregister(&sunxi_rsb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) bus_unregister(&sunxi_rsb_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) module_exit(sunxi_rsb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) MODULE_DESCRIPTION("Allwinner sunXi Reduced Serial Bus controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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