Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP3XXX L3 Interconnect Driver header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Texas Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Felipe Balbi <balbi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	sricharan <r.sricharan@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Register definitions. All 64-bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define L3_COMPONENT			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define L3_CORE				0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define L3_AGENT_CONTROL		0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define L3_AGENT_STATUS			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define L3_ERROR_LOG			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define L3_ERROR_LOG_MULTI		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define L3_ERROR_LOG_SECONDARY		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define L3_ERROR_LOG_ADDR		0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Register definitions for Sideband Interconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define L3_SI_CONTROL			0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define L3_SI_FLAG_STATUS_0		0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static const u64 shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define L3_STATUS_0_MPUIA_BRST		(shift << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define L3_STATUS_0_MPUIA_RSP		(shift << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define L3_STATUS_0_MPUIA_INBAND	(shift << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define L3_STATUS_0_IVAIA_BRST		(shift << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define L3_STATUS_0_IVAIA_RSP		(shift << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define L3_STATUS_0_IVAIA_INBAND	(shift << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define L3_STATUS_0_SGXIA_BRST		(shift << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define L3_STATUS_0_SGXIA_RSP		(shift << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define L3_STATUS_0_SGXIA_MERROR	(shift << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define L3_STATUS_0_CAMIA_BRST		(shift << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define L3_STATUS_0_CAMIA_RSP		(shift << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define L3_STATUS_0_CAMIA_INBAND	(shift << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define L3_STATUS_0_DISPIA_BRST		(shift << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define L3_STATUS_0_DISPIA_RSP		(shift << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define L3_STATUS_0_DMARDIA_BRST	(shift << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define L3_STATUS_0_DMARDIA_RSP		(shift << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define L3_STATUS_0_DMAWRIA_BRST	(shift << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define L3_STATUS_0_DMAWRIA_RSP		(shift << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define L3_STATUS_0_USBOTGIA_BRST	(shift << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define L3_STATUS_0_USBOTGIA_RSP	(shift << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define L3_STATUS_0_USBOTGIA_INBAND	(shift << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define L3_STATUS_0_USBHOSTIA_BRST	(shift << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define L3_STATUS_0_USBHOSTIA_INBAND	(shift << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define L3_STATUS_0_SMSTA_REQ		(shift << 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define L3_STATUS_0_GPMCTA_REQ		(shift << 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define L3_STATUS_0_OCMRAMTA_REQ	(shift << 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define L3_STATUS_0_OCMROMTA_REQ	(shift << 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define L3_STATUS_0_IVATA_REQ		(shift << 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define L3_STATUS_0_SGXTA_REQ		(shift << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define L3_STATUS_0_SGXTA_SERROR	(shift << 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define L3_STATUS_0_GPMCTA_SERROR	(shift << 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define L3_STATUS_0_L4CORETA_REQ	(shift << 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define L3_STATUS_0_L4PERTA_REQ		(shift << 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define L3_STATUS_0_L4EMUTA_REQ		(shift << 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define L3_STATUS_0_MAD2DTA_REQ		(shift << 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define L3_STATUS_0_TIMEOUT_MASK	(L3_STATUS_0_MPUIA_BRST		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 					| L3_STATUS_0_MPUIA_RSP		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					| L3_STATUS_0_IVAIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					| L3_STATUS_0_IVAIA_RSP		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					| L3_STATUS_0_SGXIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					| L3_STATUS_0_SGXIA_RSP		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					| L3_STATUS_0_CAMIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					| L3_STATUS_0_CAMIA_RSP		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					| L3_STATUS_0_DISPIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					| L3_STATUS_0_DISPIA_RSP	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					| L3_STATUS_0_DMARDIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 					| L3_STATUS_0_DMARDIA_RSP	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 					| L3_STATUS_0_DMAWRIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 					| L3_STATUS_0_DMAWRIA_RSP	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					| L3_STATUS_0_USBOTGIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					| L3_STATUS_0_USBOTGIA_RSP	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					| L3_STATUS_0_USBHOSTIA_BRST	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					| L3_STATUS_0_SMSTA_REQ		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					| L3_STATUS_0_GPMCTA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					| L3_STATUS_0_OCMRAMTA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					| L3_STATUS_0_OCMROMTA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					| L3_STATUS_0_IVATA_REQ		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					| L3_STATUS_0_SGXTA_REQ		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 					| L3_STATUS_0_L4CORETA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 					| L3_STATUS_0_L4PERTA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 					| L3_STATUS_0_L4EMUTA_REQ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 					| L3_STATUS_0_MAD2DTA_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define L3_SI_FLAG_STATUS_1		0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define L3_STATUS_1_MPU_DATAIA		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define L3_STATUS_1_DAPIA0		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define L3_STATUS_1_DAPIA1		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define L3_STATUS_1_IVAIA		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define L3_PM_ERROR_LOG			0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define L3_PM_CONTROL			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define L3_PM_ERROR_CLEAR_SINGLE	0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define L3_PM_ERROR_CLEAR_MULTI		0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define L3_PM_REQ_INFO_PERMISSION(n)	(0x048 + (0x020 * n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define L3_PM_READ_PERMISSION(n)	(0x050 + (0x020 * n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define L3_PM_WRITE_PERMISSION(n)	(0x058 + (0x020 * n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define L3_PM_ADDR_MATCH(n)		(0x060 + (0x020 * n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* L3 error log bit fields. Common for IA and TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define L3_ERROR_LOG_CODE		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define L3_ERROR_LOG_INITID		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define L3_ERROR_LOG_CMD		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* L3 agent status bit fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define L3_AGENT_STATUS_CLEAR_IA	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define L3_AGENT_STATUS_CLEAR_TA	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP34xx_IRQ_L3_APP		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define L3_APPLICATION_ERROR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define L3_DEBUG_ERROR			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum omap3_l3_initiator_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* LCD has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	OMAP_L3_LCD = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* SAD2D has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	OMAP_L3_SAD2D = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* MPU has 5 IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	OMAP_L3_IA_MPU_SS_1 = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	OMAP_L3_IA_MPU_SS_2 = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	OMAP_L3_IA_MPU_SS_3 = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	OMAP_L3_IA_MPU_SS_4 = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	OMAP_L3_IA_MPU_SS_5 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* IVA2.2 SS has 3 IDs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	OMAP_L3_IA_IVA_SS_1 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	OMAP_L3_IA_IVA_SS_2 = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	OMAP_L3_IA_IVA_SS_3 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* IVA 2.2 SS DMA has 6 IDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	OMAP_L3_IA_IVA_SS_DMA_1 = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	OMAP_L3_IA_IVA_SS_DMA_2 = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	OMAP_L3_IA_IVA_SS_DMA_3 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	OMAP_L3_IA_IVA_SS_DMA_4 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	OMAP_L3_IA_IVA_SS_DMA_5 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	OMAP_L3_IA_IVA_SS_DMA_6 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* SGX has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	OMAP_L3_IA_SGX = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* CAM has 3 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	OMAP_L3_IA_CAM_1 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	OMAP_L3_IA_CAM_2 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	OMAP_L3_IA_CAM_3 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* DAP has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	OMAP_L3_IA_DAP = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* SDMA WR has 2 IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	OMAP_L3_SDMA_WR_1 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	OMAP_L3_SDMA_WR_2 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* SDMA RD has 4 IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	OMAP_L3_SDMA_RD_1 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	OMAP_L3_SDMA_RD_2 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	OMAP_L3_SDMA_RD_3 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	OMAP_L3_SDMA_RD_4 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* HSUSB OTG has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	OMAP_L3_USBOTG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* HSUSB HOST has 1 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	OMAP_L3_USBHOST = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum omap3_l3_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	OMAP_L3_CODE_NOERROR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	OMAP_L3_CODE_UNSUP_CMD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	OMAP_L3_CODE_ADDR_HOLE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	OMAP_L3_CODE_PROTECT_VIOLATION = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	OMAP_L3_CODE_IN_BAND_ERR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* codes 5 and 6 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* codes 9 - 15 are also reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct omap3_l3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct clk *ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* memory base*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	void __iomem *rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int debug_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int app_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* true when and inband functional error occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned inband:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* offsets for l3 agents in order with the Flag status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned int omap3_l3_app_bases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* MPU IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* IVA 2.2 IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* SGX IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	0x1c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	0x1c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* CAMERA IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	0x5800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	0x5800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	0x5800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* DISPLAY IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	0x5400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	0x5400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/*SDMA RD IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	0x4c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	0x4c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* SDMA WR IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	0x5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* USB OTG IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	0x4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	0x4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	0x4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* USB HOST IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* SAD2D IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* SMA TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* GPMC TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	0x2400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* OCM RAM TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	0x2800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* OCM ROM TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	0x2C00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* L4 CORE TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	0x6800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* L4 PER TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	0x6c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* IVA 2.2 TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* SGX TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	0x6400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* L4 EMU TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	0x7000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* GPMC TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	0x2400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* L4 CORE TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	0x6800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* L4 PER TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	0x6c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* L4 EMU TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	0x7000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* MAD2D TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	0x3400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static unsigned int omap3_l3_debug_bases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* MPU DATA IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* DAP IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	0x5c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	0x5c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* IVA 2.2 IA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* REST RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static u32 *omap3_l3_bases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	omap3_l3_app_bases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	omap3_l3_debug_bases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * REVISIT define __raw_readll/__raw_writell here, but move them to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * <asm/io.h> at some point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define __raw_writell(v, a)	(__chk_io_ptr(a), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				*(volatile u64 __force *)(a) = (v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define __raw_readll(a)		(__chk_io_ptr(a), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				*(volatile u64 __force *)(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif