^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * OMAP L3 Interconnect error handling driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sricharan <r.sricharan@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "omap_l3_noc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * l3_handle_target() - Handle Target specific parse and reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @l3: pointer to l3 struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @base: base address of clkdm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @flag_mux: flagmux corresponding to the event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @err_src: error source index of the slave (target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * This does the second part of the error interrupt handling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 3) Parse in the slave information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 4) Print the logged information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 5) Add dump stack to provide kernel trace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 6) Clear the source if known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This handles two types of errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 1) Custom errors in L3 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Target like DMM/FW/EMIF generates SRESP=ERR error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 2) Standard L3 error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * - Unsupported CMD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * L3 tries to access target while it is idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * - OCP disconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * - Address hole error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * If DSS/ISS/FDIF/USBHOSTFS access a target where they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * do not have connectivity, the error is logged in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * their default target which is DMM2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * On High Secure devices, firewall errors are possible and those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * can be trapped as well. But the trapping is implemented as part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * secure software and hence need not be implemented here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct l3_flagmux_data *flag_mux, int err_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 std_err_main, clear, masterid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 op_code, m_req_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *l3_targ_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *l3_targ_hdr, *l3_targ_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct l3_target_data *l3_targ_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct l3_masters_data *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) char *target_name, *master_name = "UN IDENTIFIED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) char *err_description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char err_string[30] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) char info_string[60] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* We DONOT expect err_src to go out of bounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BUG_ON(err_src > MAX_CLKDM_TARGETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (err_src < flag_mux->num_targ_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) l3_targ_inst = &flag_mux->l3_targ[err_src];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) target_name = l3_targ_inst->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) l3_targ_base = base + l3_targ_inst->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) target_name = L3_TARGET_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (target_name == L3_TARGET_NOT_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Read the stderrlog_main_source from clk domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) std_err_main = readl_relaxed(l3_targ_stderr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (std_err_main & CUSTOM_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case STANDARD_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err_description = "Standard";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) snprintf(err_string, sizeof(err_string),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ": At Address: 0x%08X ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) readl_relaxed(l3_targ_slvofslsb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case CUSTOM_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) err_description = "Custom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) l3_targ_mstaddr = l3_targ_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) L3_TARG_STDERRLOG_CINFO_MSTADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Nothing to be handled here as of now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* STDERRLOG_MSTADDR Stores the NTTP master address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) masterid = (readl_relaxed(l3_targ_mstaddr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (k = 0, master = l3->l3_masters; k < l3->num_masters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) k++, master++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (masterid == master->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) master_name = master->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) op_code = readl_relaxed(l3_targ_hdr) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) m_req_info = readl_relaxed(l3_targ_info) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) snprintf(info_string, sizeof(info_string),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ": %s in %s mode during %s access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (m_req_info & BIT(1)) ? "Supervisor" : "User",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (m_req_info & BIT(3)) ? "Debug" : "Functional");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WARN(true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_name(l3->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) err_description,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) master_name, target_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) l3_transaction_type[op_code],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) err_string, info_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* clear the std error log*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clear = std_err_main | CLEAR_STDERR_LOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel_relaxed(clear, l3_targ_stderr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * l3_interrupt_handler() - interrupt handler for l3 events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @irq: irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @_l3: pointer to l3 structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Interrupt Handler for L3 error detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 1) Identify the L3 clockdomain partition to which the error belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 2) Identify the slave where the error information is logged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * ... handle the slave event..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 7) if the slave is unknown, mask out the slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct omap_l3 *l3 = _l3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int inttype, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int err_src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 err_reg, mask_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *base, *mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct l3_flagmux_data *flag_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Get the Type of interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < l3->num_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Read the regerr register of the clock domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * to determine the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) base = l3->l3_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) flag_mux = l3->l3_flagmux[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err_reg = readl_relaxed(base + flag_mux->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) L3_FLAGMUX_REGERR0 + (inttype << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) err_reg &= ~(inttype ? flag_mux->mask_app_bits :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) flag_mux->mask_dbg_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Get the corresponding error and analyse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (err_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Identify the source from control status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err_src = __ffs(err_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = l3_handle_target(l3, base, flag_mux, err_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Certain plaforms may have "undocumented" status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * pending on boot. So dont generate a severe warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * here. Just mask it off to prevent the error from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * reoccuring and locking up the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(l3->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "L3 %s error: target %d mod:%d %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) inttype ? "debug" : "application",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err_src, i, "(unclearable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mask_reg = base + flag_mux->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) L3_FLAGMUX_MASK0 + (inttype << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mask_val = readl_relaxed(mask_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mask_val &= ~(1 << err_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel_relaxed(mask_val, mask_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Mark these bits as to be ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (inttype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) flag_mux->mask_app_bits |= 1 << err_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) flag_mux->mask_dbg_bits |= 1 << err_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Error found so break the for loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) inttype ? "debug" : "application");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct of_device_id l3_noc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_DEVICE_TABLE(of, l3_noc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int omap_l3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct omap_l3 *l3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret, i, res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) of_id = of_match_device(l3_noc_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(&pdev->dev, "OF data missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!l3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) memcpy(l3, of_id->data, sizeof(*l3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) l3->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) platform_set_drvdata(pdev, l3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Get mem resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* First entry cannot be submodule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) BUG_ON(i == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) l3->l3_base[i] = l3->l3_base[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (IS_ERR(l3->l3_base[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(l3->dev, "ioremap %d failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(l3->l3_base[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) res_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Setup interrupt Handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) l3->debug_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IRQF_NO_THREAD, "l3-dbg-irq", l3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(l3->dev, "request_irq failed for %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) l3->debug_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) l3->app_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IRQF_NO_THREAD, "l3-app-irq", l3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * l3_resume_noirq() - resume function for l3_noc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @dev: pointer to l3_noc device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * We only have the resume handler only since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * have already maintained the delta register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * configuration as part of configuring the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int l3_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct omap_l3 *l3 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct l3_flagmux_data *flag_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __iomem *base, *mask_regx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 mask_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i < l3->num_modules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) base = l3->l3_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) flag_mux = l3->l3_flagmux[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (L3_APPLICATION_ERROR << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mask_val = readl_relaxed(mask_regx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mask_val &= ~(flag_mux->mask_app_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel_relaxed(mask_val, mask_regx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (L3_DEBUG_ERROR << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mask_val = readl_relaxed(mask_regx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mask_val &= ~(flag_mux->mask_dbg_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel_relaxed(mask_val, mask_regx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Dummy read to force OCP barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (mask_regx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (void)readl(mask_regx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct dev_pm_ops l3_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define L3_DEV_PM_OPS (&l3_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define L3_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct platform_driver omap_l3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .probe = omap_l3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "omap_l3_noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .pm = L3_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .of_match_table = of_match_ptr(l3_noc_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int __init omap_l3_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return platform_driver_register(&omap_l3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) postcore_initcall_sync(omap_l3_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void __exit omap_l3_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) platform_driver_unregister(&omap_l3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) module_exit(omap_l3_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_AUTHOR("Santosh Shilimkar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_AUTHOR("Sricharan R");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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