^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 370/XP, Dove, Orion5x and MV78xx0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The Marvell EBU SoCs have a configurable physical address space:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the physical address at which certain devices (PCIe, NOR, NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * etc.) sit can be configured. The configuration takes place through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * two sets of registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - One to configure the access of the CPU to the devices. Depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * on the families, there are between 8 and 20 configurable windows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * each can be use to create a physical memory window that maps to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * specific device. Devices are identified by a tuple (target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * attribute).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - One to configure the access to the CPU to the SDRAM. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * either 2 (for Dove) or 4 (for other families) windows to map the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * SDRAM into the physical address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Reads out the SDRAM address decoding windows at initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * time, and fills the mvebu_mbus_dram_info structure with these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * informations. The exported function mv_mbus_dram_info() allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * device drivers to get those informations related to the SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * address decoding windows. This is because devices also have their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * own windows (configured through registers that are part of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * device register space), and therefore the drivers for Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * devices have to configure those device -> SDRAM windows to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * that DMA works properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * - Provides an API for platform code or device drivers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * dynamically add or remove address decoding windows for the CPU ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * device accesses. This API is mvebu_mbus_add_window_by_id(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * mvebu_mbus_add_window_remap_by_id() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * mvebu_mbus_del_window().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * see the list of CPU -> SDRAM windows and their configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * (file 'sdram') and the list of CPU -> devices windows and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * configuration (file 'devices').
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * DDR target is the same on all platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TARGET_DDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * CPU Address Decode Windows registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WIN_CTRL_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WIN_CTRL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Only on HW I/O coherency capable platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WIN_CTRL_SYNCBARRIER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WIN_CTRL_TGT_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WIN_CTRL_TGT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WIN_CTRL_ATTR_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WIN_CTRL_ATTR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define WIN_CTRL_SIZE_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WIN_CTRL_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WIN_BASE_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WIN_BASE_LOW 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WIN_BASE_HIGH 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WIN_REMAP_LO_OFF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WIN_REMAP_LOW 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WIN_REMAP_HI_OFF 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UNIT_SYNC_BARRIER_OFF 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UNIT_SYNC_BARRIER_ALL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ATTR_HW_COHERENCY (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DDR_BASE_CS_HIGH_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DDR_BASE_CS_LOW_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DDR_SIZE_ENABLED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DDR_SIZE_CS_MASK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DDR_SIZE_CS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DDR_SIZE_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Relative to mbusbridge_base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MBUS_BRIDGE_CTRL_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MBUS_BRIDGE_BASE_OFF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Maximum number of windows, for all known platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MBUS_WINS_MAX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mvebu_mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mvebu_mbus_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int num_wins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool has_mbus_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int (*win_cfg_offset)(const int win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int (*win_remap_offset)(const int win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void (*setup_cpu_target)(struct mvebu_mbus_state *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int (*save_cpu_target)(struct mvebu_mbus_state *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 __iomem *store_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int (*show_cpu_target)(struct mvebu_mbus_state *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct seq_file *seq, void *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Used to store the state of one MBus window accross suspend/resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mvebu_mbus_win_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 remap_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 remap_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mvebu_mbus_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *mbuswins_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void __iomem *sdramwins_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *mbusbridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) phys_addr_t sdramwins_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct dentry *debugfs_sdram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dentry *debugfs_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct resource pcie_mem_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct resource pcie_io_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct mvebu_mbus_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int hw_io_coherency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Used during suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 mbus_bridge_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 mbus_bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct mvebu_mbus_state mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * We provide two variants of the mv_mbus_dram_info() function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * - The normal one, where the described DRAM ranges may overlap with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * the I/O windows, but for which the DRAM ranges are guaranteed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * have a power of two size. Such ranges are suitable for the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * masters that only DMA between the RAM and the device, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * actually all devices except the crypto engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * - The 'nooverlap' one, where the described DRAM ranges are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * guaranteed to not overlap with the I/O windows, but for which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * DRAM ranges will not have power of two sizes. They will only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * aligned on a 64 KB boundary, and have a size multiple of 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * KB. Such ranges are suitable for the DMA masters that DMA between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * the crypto SRAM (which is mapped through an I/O window) and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * device. This is the case for the crypto engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct mbus_dram_target_info mvebu_mbus_dram_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct mbus_dram_target_info *mv_mbus_dram_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return &mvebu_mbus_dram_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return &mvebu_mbus_dram_info_nooverlap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Checks whether the given window has remap capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Functions to manipulate the address decoding windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int win, int *enabled, u64 *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 *size, u8 *target, u8 *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 *remap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *addr = mbus->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mbus->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 basereg = readl(addr + WIN_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!(ctrlreg & WIN_CTRL_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *base |= (basereg & WIN_BASE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (remap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (mvebu_mbus_window_is_remappable(mbus, win)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 remap_low, remap_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void __iomem *addr_rmp = mbus->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mbus->soc->win_remap_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *remap = ((u64)remap_hi << 32) | remap_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *remap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel(0, addr + WIN_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(0, addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (mvebu_mbus_window_is_remappable(mbus, win)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(0, addr + WIN_REMAP_LO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(0, addr + WIN_REMAP_HI_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Checks whether the given window number is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void __iomem *addr = mbus->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mbus->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 ctrl = readl(addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return !(ctrl & WIN_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Checks whether the given (base, base+size) area doesn't overlap an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * existing region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) phys_addr_t base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 target, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u64 end = (u64)base + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (win = 0; win < mbus->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u64 wbase, wend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 wtarget, wattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mvebu_mbus_read_window(mbus, win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &enabled, &wbase, &wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &wtarget, &wattr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) wend = wbase + wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Check if the current window overlaps with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * proposed physical range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if ((u64)base < wend && end > wbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) phys_addr_t base, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (win = 0; win < mbus->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u64 wbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mvebu_mbus_read_window(mbus, win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &enabled, &wbase, &wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (base == wbase && size == wsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int win, phys_addr_t base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) phys_addr_t remap, u8 target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void __iomem *addr = mbus->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mbus->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 ctrl, remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!is_power_of_2(size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WARN(true, "Invalid MBus window size: 0x%zx\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if ((base & (phys_addr_t)(size - 1)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (attr << WIN_CTRL_ATTR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (target << WIN_CTRL_TGT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) WIN_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (mbus->hw_io_coherency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ctrl |= WIN_CTRL_SYNCBARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(ctrl, addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (mvebu_mbus_window_is_remappable(mbus, win)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *addr_rmp = mbus->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mbus->soc->win_remap_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (remap == MVEBU_MBUS_NO_REMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) remap_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) remap_addr = remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel(0, addr_rmp + WIN_REMAP_HI_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) phys_addr_t base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) phys_addr_t remap, u8 target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (remap == MVEBU_MBUS_NO_REMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (win = 0; win < mbus->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (mvebu_mbus_window_is_remappable(mbus, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (mvebu_mbus_window_is_free(mbus, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return mvebu_mbus_setup_window(mbus, win, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) size, remap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (win = 0; win < mbus->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Skip window if need remap but is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if ((remap != MVEBU_MBUS_NO_REMAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) !mvebu_mbus_window_is_remappable(mbus, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (mvebu_mbus_window_is_free(mbus, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return mvebu_mbus_setup_window(mbus, win, base, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) remap, target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Debugfs debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!(sizereg & DDR_SIZE_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) seq_printf(seq, "[%d] disabled\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) base |= basereg & DDR_BASE_CS_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) size = (sizereg | ~DDR_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) i, (unsigned long long)base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) (unsigned long long)base + size + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Special function for Dove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!(map & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) seq_printf(seq, "[%d] disabled\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) base = map & 0xff800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i, (unsigned long long)base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) (unsigned long long)base + size, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct mvebu_mbus_state *mbus = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return mbus->soc->show_cpu_target(mbus, seq, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return single_open(file, mvebu_sdram_debug_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct file_operations mvebu_sdram_debug_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .open = mvebu_sdram_debug_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct mvebu_mbus_state *mbus = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (win = 0; win < mbus->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u64 wbase, wremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 wtarget, wattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mvebu_mbus_read_window(mbus, win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &enabled, &wbase, &wsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &wtarget, &wattr, &wremap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) seq_printf(seq, "[%02d] disabled\n", win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) win, (unsigned long long)wbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) (unsigned long long)(wbase + wsize), wtarget, wattr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!is_power_of_2(wsize) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ((wbase & (u64)(wsize - 1)) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) seq_puts(seq, " (Invalid base/size!!)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (mvebu_mbus_window_is_remappable(mbus, win)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) seq_printf(seq, " (remap %016llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) (unsigned long long)wremap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) seq_printf(seq, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return single_open(file, mvebu_devs_debug_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct file_operations mvebu_devs_debug_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .open = mvebu_devs_debug_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * SoC-specific functions and definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static unsigned int generic_mbus_win_cfg_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return win << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* The register layout is a bit annoying and the below code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * tries to cope with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * - At offset 0x0, there are the registers for the first 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * windows, with 4 registers of 32 bits per window (ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * base, remap low, remap high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * - Then at offset 0x80, there is a hole of 0x10 bytes for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * the internal registers base address and internal units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * sync barrier register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * - Then at offset 0x90, there the registers for 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * windows, with only 2 registers of 32 bits per window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * (ctrl, base).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (win < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return win << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0x90 + ((win - 8) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (win < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return win << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0x900 + ((win - 8) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static unsigned int generic_mbus_win_remap_2_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (win < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return generic_mbus_win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return MVEBU_MBUS_NO_REMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static unsigned int generic_mbus_win_remap_4_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (win < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return generic_mbus_win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return MVEBU_MBUS_NO_REMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static unsigned int generic_mbus_win_remap_8_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (win < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return generic_mbus_win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return MVEBU_MBUS_NO_REMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static unsigned int armada_xp_mbus_win_remap_offset(int win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (win < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return generic_mbus_win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) else if (win == 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0xF0 - WIN_REMAP_LO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return MVEBU_MBUS_NO_REMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Use the memblock information to find the MBus bridge hole in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * physical address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) phys_addr_t reg_start, reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) uint64_t i, s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for_each_mem_range(i, ®_start, ®_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * This part of the memory is above 4 GB, so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * care for the MBus bridge hole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (reg_start >= 0x100000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * The MBus bridge hole is at the end of the RAM under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * the 4 GB limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (reg_end > s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) s = reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *start = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *end = 0x100000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * This function fills in the mvebu_mbus_dram_info_nooverlap data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * structure, by looking at the mvebu_mbus_dram_info data, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * removing the parts of it that overlap with I/O windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) uint64_t mbus_bridge_base, mbus_bridge_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int cs_nooverlap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct mbus_dram_window *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u64 base, size, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) w = &mvebu_mbus_dram_info.cs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) base = w->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) size = w->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) end = base + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * The CS is fully enclosed inside the MBus bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * area, so ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (base >= mbus_bridge_base && end <= mbus_bridge_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Beginning of CS overlaps with end of MBus, raise CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * base address, and shrink its size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (base >= mbus_bridge_base && end > mbus_bridge_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) size -= mbus_bridge_end - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) base = mbus_bridge_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * End of CS overlaps with beginning of MBus, shrink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * CS size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (base < mbus_bridge_base && end > mbus_bridge_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) size -= end - mbus_bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) w->cs_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) w->mbus_attr = 0xf & ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (mbus->hw_io_coherency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) w->mbus_attr |= ATTR_HW_COHERENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) w->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) w->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = 0, cs = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * We only take care of entries for which the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * select is enabled, and that don't have high base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * address bits set (devices can only access the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * 32 bits of the memory).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((size & DDR_SIZE_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) !(base & DDR_BASE_CS_HIGH_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct mbus_dram_window *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) w = &mvebu_mbus_dram_info.cs[cs++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) w->cs_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) w->mbus_attr = 0xf & ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (mbus->hw_io_coherency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) w->mbus_attr |= ATTR_HW_COHERENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) w->base = base & DDR_BASE_CS_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mvebu_mbus_dram_info.num_cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 __iomem *store_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) writel(base, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writel(size, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* We've written 16 words to the store address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0, cs = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Chip select enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (map & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct mbus_dram_window *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) w = &mvebu_mbus_dram_info.cs[cs++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) w->cs_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) w->mbus_attr = 0; /* CS address decoding done inside */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* the DDR controller, no need to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* provide attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) w->base = map & 0xff800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mvebu_mbus_dram_info.num_cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 __iomem *store_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writel(map, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* We've written 4 words to the store address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .num_wins = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .has_mbus_bridge = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .win_remap_offset = generic_mbus_win_remap_8_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .num_wins = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .has_mbus_bridge = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .win_remap_offset = armada_xp_mbus_win_remap_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .num_wins = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .win_cfg_offset = generic_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .win_remap_offset = generic_mbus_win_remap_4_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct mvebu_mbus_soc_data dove_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .num_wins = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .win_cfg_offset = generic_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .win_remap_offset = generic_mbus_win_remap_4_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .show_cpu_target = mvebu_sdram_debug_show_dove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * Some variants of Orion5x have 4 remappable windows, some other have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * only two of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .num_wins = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .win_cfg_offset = generic_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .win_remap_offset = generic_mbus_win_remap_4_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .num_wins = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .win_cfg_offset = generic_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .win_remap_offset = generic_mbus_win_remap_2_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .num_wins = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .win_remap_offset = generic_mbus_win_remap_8_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .show_cpu_target = mvebu_sdram_debug_show_orion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct of_device_id of_mvebu_mbus_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { .compatible = "marvell,armada370-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .data = &armada_370_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) { .compatible = "marvell,armada375-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .data = &armada_xp_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { .compatible = "marvell,armada380-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .data = &armada_xp_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) { .compatible = "marvell,armadaxp-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .data = &armada_xp_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { .compatible = "marvell,kirkwood-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .data = &kirkwood_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { .compatible = "marvell,dove-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .data = &dove_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { .compatible = "marvell,orion5x-88f5281-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .data = &orion5x_4win_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { .compatible = "marvell,orion5x-88f5182-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .data = &orion5x_2win_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { .compatible = "marvell,orion5x-88f5181-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .data = &orion5x_2win_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) { .compatible = "marvell,orion5x-88f6183-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .data = &orion5x_4win_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { .compatible = "marvell,mv78xx0-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .data = &mv78xx0_mbus_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Public API of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int mvebu_mbus_add_window_remap_by_id(unsigned int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) phys_addr_t base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) phys_addr_t remap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct mvebu_mbus_state *s = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pr_err("cannot add window '%x:%x', conflicts with another window\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) target, attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) phys_addr_t base, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) size, MVEBU_MBUS_NO_REMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int mvebu_mbus_del_window(phys_addr_t base, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) win = mvebu_mbus_find_window(&mbus_state, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (win < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mvebu_mbus_disable_window(&mbus_state, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *res = mbus_state.pcie_mem_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) *res = mbus_state.pcie_io_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) const struct mbus_dram_target_info *dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Get dram info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dram = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!dram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pr_err("missing DRAM information\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Try to find matching DRAM window for phyaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (cs->base <= phyaddr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) phyaddr <= (cs->base + cs->size - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) *target = dram->mbus_dram_target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *attr = cs->mbus_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pr_err("invalid dram address %pa\n", &phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) for (win = 0; win < mbus_state.soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u64 wbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) size, target, attr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (wbase <= phyaddr && phyaddr <= wbase + *size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static __init int mvebu_mbus_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct mvebu_mbus_state *s = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * If no base has been initialized, doesn't make sense to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * register the debugfs entries. We may be on a multiplatform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * kernel that isn't running a Marvell EBU SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!s->mbuswins_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (s->debugfs_root) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) s->debugfs_root, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &mvebu_sdram_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) s->debugfs_root, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) &mvebu_devs_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) fs_initcall(mvebu_mbus_debugfs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int mvebu_mbus_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct mvebu_mbus_state *s = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!s->mbusbridge_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) for (win = 0; win < s->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) void __iomem *addr = s->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) s->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void __iomem *addr_rmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) s->wins[win].base = readl(addr + WIN_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (!mvebu_mbus_window_is_remappable(s, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) addr_rmp = s->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) s->soc->win_remap_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) MBUS_BRIDGE_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) s->mbus_bridge_base = readl(s->mbusbridge_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) MBUS_BRIDGE_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static void mvebu_mbus_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct mvebu_mbus_state *s = &mbus_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel(s->mbus_bridge_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) writel(s->mbus_bridge_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (win = 0; win < s->soc->num_wins; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) void __iomem *addr = s->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) s->soc->win_cfg_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) void __iomem *addr_rmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) writel(s->wins[win].base, addr + WIN_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!mvebu_mbus_window_is_remappable(s, win))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) addr_rmp = s->mbuswins_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) s->soc->win_remap_offset(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static struct syscore_ops mvebu_mbus_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .suspend = mvebu_mbus_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .resume = mvebu_mbus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) phys_addr_t mbuswins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) size_t mbuswins_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) phys_addr_t sdramwins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) size_t sdramwins_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) phys_addr_t mbusbridge_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) size_t mbusbridge_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) bool is_coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) int win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (!mbus->mbuswins_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!mbus->sdramwins_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) iounmap(mbus_state.mbuswins_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mbus->sdramwins_phys_base = sdramwins_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (mbusbridge_phys_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) mbusbridge_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!mbus->mbusbridge_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) iounmap(mbus->sdramwins_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) iounmap(mbus->mbuswins_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) mbus->mbusbridge_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) for (win = 0; win < mbus->soc->num_wins; win++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mvebu_mbus_disable_window(mbus, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mbus->soc->setup_cpu_target(mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mvebu_mbus_setup_cpu_target_nooverlap(mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (is_coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) writel(UNIT_SYNC_BARRIER_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) register_syscore_ops(&mvebu_mbus_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) size_t mbuswins_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) phys_addr_t sdramwins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) size_t sdramwins_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (!strcmp(of_id->compatible, soc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (!of_id->compatible[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pr_err("could not find a matching SoC family\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) mbus_state.soc = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return mvebu_mbus_common_init(&mbus_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mbuswins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) mbuswins_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) sdramwins_phys_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sdramwins_size, 0, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * The window IDs in the ranges DT property have the following format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * - bits 28 to 31: MBus custom field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * - bits 24 to 27: window target ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * - bits 16 to 23: window attribute ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * - bits 0 to 15: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define TARGET(id) (((id) & 0x0F000000) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define ATTR(id) (((id) & 0x00FF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u32 base, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) u8 target, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) target, attr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pr_err("cannot add window '%04x:%04x', too many windows\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mbus_parse_ranges(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int *addr_cells, int *c_addr_cells, int *c_size_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int *cell_count, const __be32 **ranges_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) const __be32 **ranges_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int ranges_len, tuple_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Allow a node with no 'ranges' property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) *ranges_start = of_get_property(node, "ranges", &ranges_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (*ranges_start == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) *ranges_start = *ranges_end = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) *addr_cells = of_n_addr_cells(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) prop = of_get_property(node, "#address-cells", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) *c_addr_cells = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) prop = of_get_property(node, "#size-cells", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) *c_size_cells = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) tuple_len = (*cell_count) * sizeof(__be32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ranges_len % tuple_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pr_warn("malformed ranges entry '%pOFn'\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int addr_cells, c_addr_cells, c_size_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int i, ret, cell_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) const __be32 *r, *ranges_start, *ranges_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) &c_size_cells, &cell_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) &ranges_start, &ranges_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u32 windowid, base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u8 target, attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * An entry with a non-zero custom field do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * correspond to a static window, so skip it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) windowid = of_read_number(r, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (CUSTOM(windowid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) target = TARGET(windowid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) attr = ATTR(windowid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) base = of_read_number(r + c_addr_cells, addr_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) size = of_read_number(r + c_addr_cells + addr_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) c_size_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ret = mbus_dt_setup_win(mbus, base, size, target, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct resource *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct resource *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u32 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * These are optional, so we make sure that resource_size(x) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) memset(mem, 0, sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mem->end = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) memset(io, 0, sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) io->end = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mem->start = reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) mem->end = mem->start + reg[1] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) mem->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) io->start = reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) io->end = io->start + reg[1] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) io->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int __init mvebu_mbus_dt_init(bool is_coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct device_node *np, *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) pr_err("could not find a matching SoC family\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) mbus_state.soc = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) prop = of_get_property(np, "controller", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pr_err("required 'controller' property missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) controller = of_find_node_by_phandle(be32_to_cpup(prop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!controller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pr_err("could not find an 'mbus-controller' node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (of_address_to_resource(controller, 0, &mbuswins_res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pr_err("cannot get MBUS register address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (of_address_to_resource(controller, 1, &sdramwins_res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pr_err("cannot get SDRAM register address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Set the resource to 0 so that it can be left unmapped by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * mvebu_mbus_common_init() if the DT doesn't carry the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * necessary information. This is needed to preserve backward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (mbus_state.soc->has_mbus_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (of_address_to_resource(controller, 2, &mbusbridge_res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) mbus_state.hw_io_coherency = is_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* Get optional pcie-{mem,io}-aperture properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) &mbus_state.pcie_io_aperture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = mvebu_mbus_common_init(&mbus_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mbuswins_res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) resource_size(&mbuswins_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) sdramwins_res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) resource_size(&sdramwins_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mbusbridge_res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) resource_size(&mbusbridge_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) is_coherent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Setup statically declared windows in the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return mbus_dt_setup(&mbus_state, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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