Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * EIM driver for Freescale's i.MX chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct imx_weim_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	unsigned int	cs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	unsigned int	cs_regs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	unsigned int	cs_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int	wcr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int	wcr_bcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct imx_weim_devtype imx1_weim_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.cs_count	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.cs_regs_count	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.cs_stride	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct imx_weim_devtype imx27_weim_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.cs_count	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.cs_regs_count	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.cs_stride	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct imx_weim_devtype imx50_weim_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.cs_count	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.cs_regs_count	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.cs_stride	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.wcr_offset	= 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.wcr_bcm	= BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const struct imx_weim_devtype imx51_weim_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.cs_count	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.cs_regs_count	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.cs_stride	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MAX_CS_REGS_COUNT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX_CS_COUNT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OF_REG_SIZE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct cs_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	bool is_applied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 regs[MAX_CS_REGS_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct cs_timing_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct cs_timing cs[MAX_CS_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static const struct of_device_id weim_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* i.MX1/21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* i.MX25/27/31/35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* i.MX50/53/6Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* i.MX51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) MODULE_DEVICE_TABLE(of, weim_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int imx_weim_gpr_setup(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 gprvals[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		05,	/* CS0(128M) CS1(0M)  CS2(0M)  CS3(0M)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		033,	/* CS0(64M)  CS1(64M) CS2(0M)  CS3(0M)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		0113,	/* CS0(64M)  CS1(32M) CS2(32M) CS3(0M)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		01111,	/* CS0(32M)  CS1(32M) CS2(32M) CS3(32M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 gprval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	of_property_for_each_u32(np, "ranges", prop, p, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (i % 4 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			cs = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		} else if (i % 4 == 3 && val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			val = (val / SZ_32M) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			gprval |= val << cs * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (i == 0 || i % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (gprval == gprvals[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Parse and set the timing for this device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int weim_timing_setup(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			     struct device_node *np, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			     const struct imx_weim_devtype *devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			     struct cs_timing_state *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 cs_idx, value[MAX_CS_REGS_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int reg_idx, num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct cs_timing *cst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					 value, devtype->cs_regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * the child node's "reg" property may contain multiple address ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * extract the chip select for each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (num_regs < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!num_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/* get the CS index from this child node's "reg" property. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ret = of_property_read_u32_index(np, "reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 					reg_idx * OF_REG_SIZE, &cs_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (cs_idx >= devtype->cs_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		/* prevent re-configuring a CS that's already been configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		cst = &ts->cs[cs_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (cst->is_applied && memcmp(value, cst->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					devtype->cs_regs_count * sizeof(u32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		/* set the timing for WEIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		for (i = 0; i < devtype->cs_regs_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			writel(value[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				base + cs_idx * devtype->cs_stride + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (!cst->is_applied) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			cst->is_applied = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			memcpy(cst->regs, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				devtype->cs_regs_count * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	const struct of_device_id *of_id = of_match_device(weim_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 							   &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	const struct imx_weim_devtype *devtype = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	int ret, have_child = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct cs_timing_state ts = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (devtype == &imx50_weim_devtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ret = imx_weim_gpr_setup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (devtype->wcr_bcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			reg = readl(base + devtype->wcr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			writel(reg | devtype->wcr_bcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				base + devtype->wcr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			dev_err(&pdev->dev, "burst clk mode not supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	for_each_available_child_of_node(pdev->dev.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			dev_warn(&pdev->dev, "%pOF set timing failed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			have_child = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (have_child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		ret = of_platform_default_populate(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 						   NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		dev_err(&pdev->dev, "%pOF fail to create devices.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int weim_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* get the resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* get the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* parse the device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = weim_parse_dt(pdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_info(&pdev->dev, "Driver registered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_driver weim_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.name		= "imx-weim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.of_match_table	= weim_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe = weim_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) module_platform_driver(weim_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_AUTHOR("Freescale Semiconductor Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DESCRIPTION("i.MX EIM Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_LICENSE("GPL");