^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale Management Complex (MC) bus driver MSI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: German Rivera <German.Rivera@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi_iort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "fsl-mc-private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef GENERIC_MSI_DOMAIN_OPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Generate a unique ID identifying the interrupt (only used within the MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * irqdomain. Combine the icid with the interrupt index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Make the base hwirq value for ICID*10000 so it is readable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * as a decimal value in /proc/interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return (irq_hw_number_t)(desc->fsl_mc.msi_index + (dev->icid * 10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) arg->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define fsl_mc_msi_set_desc NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * set_desc should not be set by the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!ops->set_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ops->set_desc = fsl_mc_msi_set_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct fsl_mc_device_irq *mc_dev_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct msi_desc *msi_desc = mc_dev_irq->msi_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dprc_irq_cfg irq_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * msi_desc->msg.address is 0x0 when this function is invoked in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * the free_irq() code path. In this case, for the MC, we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * really need to "unprogram" the MSI, so we just return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (msi_desc->msg.address_lo == 0x0 && msi_desc->msg.address_hi == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!owner_mc_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) msi_desc->msg.address_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irq_cfg.val = msi_desc->msg.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) irq_cfg.irq_num = msi_desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (owner_mc_dev == mc_bus_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * IRQ is for the mc_bus_dev's DPRC itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) error = dprc_set_irq(mc_bus_dev->mc_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mc_bus_dev->mc_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mc_dev_irq->dev_irq_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &irq_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(&owner_mc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "dprc_set_irq() failed: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * IRQ is for for a child device of mc_bus_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) error = dprc_set_obj_irq(mc_bus_dev->mc_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mc_bus_dev->mc_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) owner_mc_dev->obj_desc.type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) owner_mc_dev->obj_desc.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mc_dev_irq->dev_irq_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &irq_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(&owner_mc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "dprc_obj_set_irq() failed: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * NOTE: This function is invoked with interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void fsl_mc_msi_write_msg(struct irq_data *irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct fsl_mc_device_irq *mc_dev_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &mc_bus->irq_resources[msi_desc->fsl_mc.msi_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) msi_desc->msg = *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Program the MSI (paddr, value) pair in the device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct irq_chip *chip = info->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * irq_write_msi_msg should not be set by the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!chip->irq_write_msi_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) chip->irq_write_msi_msg = fsl_mc_msi_write_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @np: Optional device-tree node of the interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @info: MSI domain info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @parent: Parent irq domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Updates the domain and chip ops and creates a fsl-mc MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * interrupt domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * A domain pointer or NULL in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (WARN_ON((info->flags & MSI_FLAG_LEVEL_CAPABLE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) fsl_mc_msi_update_dom_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fsl_mc_msi_update_chip_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) domain = msi_create_irq_domain(fwnode, info, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct irq_domain *fsl_mc_find_msi_domain(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device *root_dprc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct device *bus_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) fsl_mc_get_root_dprc(dev, &root_dprc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bus_dev = root_dprc_dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (bus_dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) msi_domain = of_msi_map_get_device_domain(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mc_dev->icid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DOMAIN_BUS_FSL_MC_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * if the msi-map property is missing assume that all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * child containers inherit the domain from the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!msi_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msi_domain = of_msi_get_domain(bus_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bus_dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DOMAIN_BUS_FSL_MC_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) msi_domain = iort_get_device_domain(dev, mc_dev->icid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DOMAIN_BUS_FSL_MC_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void fsl_mc_msi_free_descs(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct msi_desc *desc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) list_del(&desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) free_msi_entry(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int fsl_mc_msi_alloc_descs(struct device *dev, unsigned int irq_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct msi_desc *msi_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (i = 0; i < irq_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) msi_desc = alloc_msi_entry(dev, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!msi_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "Failed to allocate msi entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto cleanup_msi_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) msi_desc->fsl_mc.msi_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) INIT_LIST_HEAD(&msi_desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) list_add_tail(&msi_desc->list, dev_to_msi_list(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cleanup_msi_descs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fsl_mc_msi_free_descs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int fsl_mc_msi_domain_alloc_irqs(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int irq_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!list_empty(dev_to_msi_list(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) error = fsl_mc_msi_alloc_descs(dev, irq_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msi_domain = dev_get_msi_domain(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) goto cleanup_msi_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * NOTE: Calling this function will trigger the invocation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * its_fsl_mc_msi_prepare() callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) error = msi_domain_alloc_irqs(msi_domain, dev, irq_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "Failed to allocate IRQs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto cleanup_msi_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cleanup_msi_descs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) fsl_mc_msi_free_descs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void fsl_mc_msi_domain_free_irqs(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msi_domain = dev_get_msi_domain(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!msi_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) msi_domain_free_irqs(msi_domain, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (list_empty(dev_to_msi_list(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) fsl_mc_msi_free_descs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }