^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI da8xx master peripheral priority driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 BayLibre SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * REVISIT: Linux doesn't have a good framework for the kind of performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * knobs this driver controls. We can't use device tree properties as it deals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * with hardware configuration rather than description. We also don't want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * commit to maintaining some random sysfs attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * For now we just hardcode the register values for the boards that need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * some changes (as is the case for the LCD controller on da850-lcdk - the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * first board we support here). When linux gets an appropriate framework,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * we'll easily convert the driver to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DA8XX_MSTPRI0_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DA8XX_MSTPRI1_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DA8XX_MSTPRI2_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DA8XX_MSTPRI_ARM_I = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DA8XX_MSTPRI_ARM_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DA8XX_MSTPRI_UPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DA8XX_MSTPRI_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DA8XX_MSTPRI_PRU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DA8XX_MSTPRI_PRU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DA8XX_MSTPRI_EDMA30TC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DA8XX_MSTPRI_EDMA30TC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DA8XX_MSTPRI_EDMA31TC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DA8XX_MSTPRI_VPIF_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DA8XX_MSTPRI_VPIF_DMA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DA8XX_MSTPRI_EMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DA8XX_MSTPRI_USB0CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DA8XX_MSTPRI_USB0CDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DA8XX_MSTPRI_UHPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DA8XX_MSTPRI_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DA8XX_MSTPRI_LCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct da8xx_mstpri_descr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct da8xx_mstpri_descr da8xx_mstpri_priority_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [DA8XX_MSTPRI_ARM_I] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .reg = DA8XX_MSTPRI0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .mask = 0x0000000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [DA8XX_MSTPRI_ARM_D] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg = DA8XX_MSTPRI0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .mask = 0x000000f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [DA8XX_MSTPRI_UPP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .reg = DA8XX_MSTPRI0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mask = 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [DA8XX_MSTPRI_SATA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg = DA8XX_MSTPRI0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mask = 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [DA8XX_MSTPRI_PRU0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mask = 0x0000000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [DA8XX_MSTPRI_PRU1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mask = 0x000000f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [DA8XX_MSTPRI_EDMA30TC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .mask = 0x00000f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [DA8XX_MSTPRI_EDMA30TC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .mask = 0x0000f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [DA8XX_MSTPRI_EDMA31TC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .mask = 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [DA8XX_MSTPRI_VPIF_DMA_0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .mask = 0x0f000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [DA8XX_MSTPRI_VPIF_DMA_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .reg = DA8XX_MSTPRI1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mask = 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [DA8XX_MSTPRI_EMAC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mask = 0x0000000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [DA8XX_MSTPRI_USB0CFG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mask = 0x00000f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [DA8XX_MSTPRI_USB0CDMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .mask = 0x0000f000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [DA8XX_MSTPRI_UHPI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .mask = 0x00f00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [DA8XX_MSTPRI_USB1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .mask = 0x0f000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [DA8XX_MSTPRI_LCDC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .reg = DA8XX_MSTPRI2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .mask = 0xf0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct da8xx_mstpri_priority {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int which;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct da8xx_mstpri_board_priorities {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct da8xx_mstpri_priority *priorities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) size_t numprio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Default memory settings of da850 do not meet the throughput/latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * requirements of tilcdc. This results in the image displayed being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * incorrect and the following warning being displayed by the LCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * drm driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * tilcdc da8xx_lcdc.0: tilcdc_crtc_irq(0x00000020): FIFO underfow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct da8xx_mstpri_priority da850_lcdk_priorities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .which = DA8XX_MSTPRI_LCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .which = DA8XX_MSTPRI_EDMA30TC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .which = DA8XX_MSTPRI_EDMA30TC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .val = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct da8xx_mstpri_board_priorities da8xx_mstpri_board_confs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .board = "ti,da850-lcdk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .priorities = da850_lcdk_priorities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .numprio = ARRAY_SIZE(da850_lcdk_priorities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct da8xx_mstpri_board_priorities *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) da8xx_mstpri_get_board_prio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct da8xx_mstpri_board_priorities *board_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < ARRAY_SIZE(da8xx_mstpri_board_confs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) board_prio = &da8xx_mstpri_board_confs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (of_machine_is_compatible(board_prio->board))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return board_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int da8xx_mstpri_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct da8xx_mstpri_board_priorities *prio_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const struct da8xx_mstpri_descr *prio_descr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct da8xx_mstpri_priority *prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void __iomem *mstpri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mstpri = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(mstpri)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "unable to map MSTPRI registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return PTR_ERR(mstpri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) prio_list = da8xx_mstpri_get_board_prio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!prio_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(dev, "no master priorities defined for this board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < prio_list->numprio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) prio = &prio_list->priorities[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) prio_descr = &da8xx_mstpri_priority_list[prio->which];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (prio_descr->reg + sizeof(u32) > resource_size(res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_warn(dev, "register offset out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg = readl(mstpri + prio_descr->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) reg &= ~prio_descr->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg |= prio->val << prio_descr->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(reg, mstpri + prio_descr->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id da8xx_mstpri_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .compatible = "ti,da850-mstpri", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct platform_driver da8xx_mstpri_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .probe = da8xx_mstpri_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "da8xx-mstpri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .of_match_table = da8xx_mstpri_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) module_platform_driver(da8xx_mstpri_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_DESCRIPTION("TI da8xx master peripheral priority driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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