^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kdebug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifdef CONFIG_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARB_ERR_CAP_CLEAR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARB_ERR_CAP_STATUS_TEA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ARB_ERR_CAP_STATUS_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARB_BP_CAP_CLEAR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARB_BP_CAP_STATUS_PROT_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARB_BP_CAP_STATUS_TYPE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARB_BP_CAP_STATUS_RSP_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ARB_BP_CAP_STATUS_BS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARB_BP_CAP_STATUS_WRITE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ARB_BP_CAP_STATUS_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ARB_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ARB_BP_CAP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ARB_BP_CAP_HI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ARB_BP_CAP_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ARB_BP_CAP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ARB_BP_CAP_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ARB_ERR_CAP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ARB_ERR_CAP_HI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ARB_ERR_CAP_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ARB_ERR_CAP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ARB_ERR_CAP_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const int gisb_offsets_bcm7038[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [ARB_TIMER] = 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [ARB_BP_CAP_CLR] = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [ARB_BP_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [ARB_BP_CAP_ADDR] = 0x0b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [ARB_BP_CAP_STATUS] = 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [ARB_BP_CAP_MASTER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [ARB_ERR_CAP_CLR] = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [ARB_ERR_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [ARB_ERR_CAP_ADDR] = 0x0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [ARB_ERR_CAP_STATUS] = 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [ARB_ERR_CAP_MASTER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const int gisb_offsets_bcm7278[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [ARB_TIMER] = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [ARB_BP_CAP_CLR] = 0x01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [ARB_BP_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [ARB_BP_CAP_ADDR] = 0x220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [ARB_BP_CAP_STATUS] = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [ARB_BP_CAP_MASTER] = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [ARB_ERR_CAP_CLR] = 0x7f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [ARB_ERR_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [ARB_ERR_CAP_ADDR] = 0x7e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [ARB_ERR_CAP_STATUS] = 0x7f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [ARB_ERR_CAP_MASTER] = 0x7f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const int gisb_offsets_bcm7400[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [ARB_TIMER] = 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [ARB_BP_CAP_CLR] = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [ARB_BP_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [ARB_BP_CAP_ADDR] = 0x0b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [ARB_BP_CAP_STATUS] = 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [ARB_BP_CAP_MASTER] = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [ARB_ERR_CAP_CLR] = 0x0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [ARB_ERR_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [ARB_ERR_CAP_ADDR] = 0x0cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [ARB_ERR_CAP_STATUS] = 0x0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [ARB_ERR_CAP_MASTER] = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const int gisb_offsets_bcm7435[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [ARB_TIMER] = 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [ARB_BP_CAP_CLR] = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [ARB_BP_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [ARB_BP_CAP_ADDR] = 0x158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [ARB_BP_CAP_STATUS] = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [ARB_BP_CAP_MASTER] = 0x164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [ARB_ERR_CAP_CLR] = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [ARB_ERR_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [ARB_ERR_CAP_ADDR] = 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [ARB_ERR_CAP_STATUS] = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [ARB_ERR_CAP_MASTER] = 0x178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const int gisb_offsets_bcm7445[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [ARB_TIMER] = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [ARB_BP_CAP_CLR] = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [ARB_BP_CAP_HI_ADDR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [ARB_BP_CAP_ADDR] = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [ARB_BP_CAP_STATUS] = 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [ARB_BP_CAP_MASTER] = 0x1e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [ARB_ERR_CAP_CLR] = 0x7e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [ARB_ERR_CAP_HI_ADDR] = 0x7e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [ARB_ERR_CAP_ADDR] = 0x7ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [ARB_ERR_CAP_STATUS] = 0x7f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [ARB_ERR_CAP_MASTER] = 0x7f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct brcmstb_gisb_arb_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const int *gisb_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct list_head next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *master_names[sizeof(u32) * BITS_PER_BYTE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 saved_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static LIST_HEAD(brcmstb_gisb_arb_device_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int offset = gdev->gisb_offsets[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (offset < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (reg == ARB_ERR_CAP_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (gdev->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ioread32be(gdev->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ioread32(gdev->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) value = gisb_read(gdev, ARB_BP_CAP_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int offset = gdev->gisb_offsets[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (gdev->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) iowrite32be(val, gdev->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iowrite32(val, gdev->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static ssize_t gisb_arb_get_timeout(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mutex_lock(&gdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) timeout = gisb_read(gdev, ARB_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mutex_unlock(&gdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return sprintf(buf, "%d", timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static ssize_t gisb_arb_set_timeout(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = kstrtoint(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (val == 0 || val >= 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mutex_lock(&gdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gisb_write(gdev, val, ARB_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mutex_unlock(&gdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 masters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 mask = gdev->valid_mask & masters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (hweight_long(mask) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return gdev->master_names[ffs(mask) - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const char *reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 cap_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 arb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const char *m_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) char m_fmt[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Invalid captured address, bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Read the address and master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) arb_addr = gisb_read_address(gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) m_name = brcmstb_gisb_master_to_str(gdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!m_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) m_name = m_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) reason, arb_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) m_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* clear the GISB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifdef CONFIG_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct brcmstb_gisb_arb_device *gdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 cap_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Invalid captured address, bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) is_fixup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct brcmstb_gisb_arb_device *gdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *m_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 bp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u64 arb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) char m_fmt[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Invalid captured address, bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Read the address and master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) arb_addr = gisb_read_bp_address(gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) master = gisb_read(gdev, ARB_BP_CAP_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) m_name = brcmstb_gisb_master_to_str(gdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!m_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) m_name = m_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) m_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* clear the GISB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Dump out gisb errors on die or panic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int dump_gisb_error(struct notifier_block *self, unsigned long v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct notifier_block gisb_die_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .notifier_call = dump_gisb_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct notifier_block gisb_panic_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .notifier_call = dump_gisb_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int dump_gisb_error(struct notifier_block *self, unsigned long v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct brcmstb_gisb_arb_device *gdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) const char *reason = "panic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (self == &gisb_die_notifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reason = "die";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* iterate over each GISB arb registered handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) brcmstb_gisb_arb_decode_addr(gdev, reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gisb_arb_get_timeout, gisb_arb_set_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct attribute *gisb_arb_sysfs_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) &dev_attr_gisb_arb_timeout.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct attribute_group gisb_arb_sysfs_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .attrs = gisb_arb_sysfs_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct brcmstb_gisb_arb_device *gdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int err, timeout_irq, tea_irq, bp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int num_masters, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int i, first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) timeout_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tea_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bp_irq = platform_get_irq(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!gdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_init(&gdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) INIT_LIST_HEAD(&gdev->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gdev->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(gdev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return PTR_ERR(gdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pr_err("failed to look up compatible string\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gdev->gisb_offsets = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gdev->big_endian = of_device_is_big_endian(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err = devm_request_irq(&pdev->dev, timeout_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) brcmstb_gisb_timeout_handler, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) err = devm_request_irq(&pdev->dev, tea_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) brcmstb_gisb_tea_handler, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Interrupt is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (bp_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = devm_request_irq(&pdev->dev, bp_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) brcmstb_gisb_bp_handler, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* If we do not have a valid mask, assume all masters are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &gdev->valid_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) gdev->valid_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Proceed with reading the litteral names if we agree on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * number of masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) num_masters = of_property_count_strings(dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "brcm,gisb-arb-master-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (hweight_long(gdev->valid_mask) == num_masters) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) first = ffs(gdev->valid_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) last = fls(gdev->valid_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = first; i < last; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!(gdev->valid_mask & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) of_property_read_string_index(dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "brcm,gisb-arb-master-names", j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &gdev->master_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) platform_set_drvdata(pdev, gdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #ifdef CONFIG_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) board_be_handler = brcmstb_bus_error_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) register_die_notifier(&gisb_die_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &gisb_panic_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_info(&pdev->dev, "registered irqs: %d, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) timeout_irq, tea_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int brcmstb_gisb_arb_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Make sure we provide the same timeout value that was configured before, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * do this before the GISB timeout interrupt handler has any chance to run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define brcmstb_gisb_arb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define brcmstb_gisb_arb_resume_noirq NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .suspend = brcmstb_gisb_arb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .resume_noirq = brcmstb_gisb_arb_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct platform_driver brcmstb_gisb_arb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = "brcm-gisb-arb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .of_match_table = brcmstb_gisb_arb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .pm = &brcmstb_gisb_arb_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int __init brcm_gisb_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return platform_driver_probe(&brcmstb_gisb_arb_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) brcmstb_gisb_arb_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) module_init(brcm_gisb_driver_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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