^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * CCI cache coherent interconnect driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/arm-cci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *cci_ctrl_base __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static unsigned long cci_ctrl_phys __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_ARM_CCI400_PORT_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cci_nb_ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int nb_ace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int nb_ace_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct cci_nb_ports cci400_ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .nb_ace = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .nb_ace_lite = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCI400_PORTS_DATA (&cci400_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCI400_PORTS_DATA (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct of_device_id arm_cci_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifdef CONFIG_ARM_CCI400_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_ARM_CCI5xx_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .compatible = "arm,cci-500", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .compatible = "arm,cci-550", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct of_dev_auxdata arm_cci_auxdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRIVER_NAME "ARM-CCI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int cci_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!cci_probed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return of_platform_populate(pdev->dev.of_node, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) arm_cci_auxdata, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct platform_driver cci_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .of_match_table = arm_cci_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .probe = cci_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int __init cci_platform_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return platform_driver_register(&cci_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_ARM_CCI400_PORT_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CCI_PORT_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CCI_CTRL_STATUS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CCI_ENABLE_SNOOP_REQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CCI_ENABLE_DVM_REQ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum cci_ace_port_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ACE_INVALID_PORT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ACE_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ACE_LITE_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct cci_ace_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum cci_ace_port_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct cci_ace_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned int nb_cci_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct cpu_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 mpidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Use the port MSB as valid flag, shift can be made dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * by computing number of bits required for port indexes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Code disabling CCI cpu ports runs with D-cache invalidated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * and SCTLR bit clear so data accesses must be kept to a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * to improve performance; for now shift is left static to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * avoid one more data access while disabling the CCI port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PORT_VALID_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PORT_VALID (0x1 << PORT_VALID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) port->port = PORT_VALID | index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) port->mpidr = mpidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline bool cpu_port_is_valid(struct cpu_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return !!(port->port & PORT_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct cpu_port cpu_port[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * __cci_ace_get_port - Function to retrieve the port index connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * a cpu or device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @dn: device node of the device to look-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @type: port type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * - CCI port index if success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * - -ENODEV if failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int __cci_ace_get_port(struct device_node *dn, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool ace_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device_node *cci_portn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < nb_cci_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ace_match = ports[i].type == type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ace_match && cci_portn == ports[i].dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int cci_ace_get_port(struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return __cci_ace_get_port(dn, ACE_LITE_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXPORT_SYMBOL_GPL(cci_ace_get_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void cci_ace_init_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int port, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device_node *cpun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Port index look-up speeds up the function disabling ports by CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * since the logical to port index mapping is done once and does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * not change after system boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * The stashed index array is initialized for all possible CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * at probe time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* too early to use cpu->of_node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpun = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (WARN(!cpun, "Missing cpu device node\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) port = __cci_ace_get_port(cpun, ACE_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (port < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) WARN(!cpu_port_is_valid(&cpu_port[cpu]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "CPU %u does not have an associated CCI port\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Functions to enable/disable a CCI interconnect slave port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * They are called by low-level power management code to disable slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * interfaces snoops and DVM broadcast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Since they may execute with cache data allocation disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * after the caches have been cleaned and invalidated the functions provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * no explicit locking since they may run with D-cache disabled, so normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * cacheable kernel locks based on ldrex/strex may not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Locking has to be provided by BSP implementations to ensure proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * cci_port_control() - function to control a CCI port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @port: index of the port to setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @enable: if true enables the port, if false disables it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void notrace cci_port_control(unsigned int port, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __iomem *base = ports[port].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This function is called from power down procedures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * and must not execute any instruction that might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * cause the processor to be put in a quiescent state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * (eg wfi). Hence, cpu_relax() can not be added to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * read loop to optimize power, since it might hide possibly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * disruptive operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @mpidr: mpidr of the CPU whose CCI port should be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Disabling a CCI port for a CPU implies disabling the CCI port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * controlling that CPU cluster. Code disabling CPU CCI ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * must make sure that the CPU running the code is the last active CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * in the cluster ie all other CPUs are quiescent in a low power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * -ENODEV on port look-up failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int notrace cci_disable_port_by_cpu(u64 mpidr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bool is_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) is_valid = cpu_port_is_valid(&cpu_port[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cci_port_control(cpu_port[cpu].port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * cci_enable_port_for_self() - enable a CCI port for calling CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Enabling a CCI port for the calling CPU implies enabling the CCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * port controlling that CPU's cluster. Caller must make sure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * CPU running the code is the first active CPU in the cluster and all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * other CPUs are quiescent in a low power state or waiting for this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * to complete the CCI initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Because this is called when the MMU is still off and with no stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * the code must be position independent and ideally rely on callee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * clobbered registers only. To achieve this we must code this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * entirely in assembler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * On success this returns with the proper CCI port enabled. In case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * any failure this never returns as the inability to enable the CCI is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * fatal and there is no possible recovery at this stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) asmlinkage void __naked cci_enable_port_for_self(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) asm volatile ("\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) " .arch armv7-a\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) " and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) " adr r1, 5f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) " ldr r2, [r1] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) " add r1, r1, r2 @ &cpu_port \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) " add ip, r1, %[sizeof_cpu_port] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Loop over the cpu_port array looking for a matching MPIDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) " cmp r2, r0 @ compare MPIDR \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) " bne 2f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Found a match, now test port validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) " ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) " tst r3, #"__stringify(PORT_VALID)" \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) " bne 3f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* no match, loop with the next cpu_port entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "2: add r1, r1, %[sizeof_struct_cpu_port] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) " cmp r1, ip @ done? \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) " blo 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* CCI port not found -- cheaply try to stall this CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "cci_port_not_found: \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) " wfi \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) " wfe \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) " b cci_port_not_found \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Use matched port index to look up the corresponding ports entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) " adr r0, 6f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) " ldmia r0, {r1, r2} \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) " sub r1, r1, r0 @ virt - phys \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) " ldr r0, [r0, r2] @ *(&ports) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) " mov r2, %[sizeof_struct_ace_port] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) " mla r0, r2, r3, r0 @ &ports[index] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) " sub r0, r0, r1 @ virt_to_phys() \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Enable the CCI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) " ldr r0, [r0, %[offsetof_port_phys]] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) " mov r3, %[cci_enable_req]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* poll the status reg for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) " adr r1, 7f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) " ldr r0, [r1] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) " ldr r0, [r0, r1] @ cci_ctrl_base \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) " tst r1, %[cci_control_status_bits] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) " bne 4b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) " mov r0, #0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) " bx lr \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) " .align 2 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "5: .word cpu_port - . \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "6: .word . \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) " .word ports - 6b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "7: .word cci_ctrl_phys - . \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [sizeof_cpu_port] "i" (sizeof(cpu_port)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [cci_control_status_bits] "i" cpu_to_le32(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifndef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * __cci_control_port_by_device() - function to control a CCI port by device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * @dn: device node pointer of the device whose CCI port should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @enable: if true enables the port, if false disables it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * -ENODEV on port look-up failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) port = __cci_ace_get_port(dn, ACE_LITE_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (WARN_ONCE(port < 0, "node %pOF ACE lite port look-up failure\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) cci_port_control(port, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * __cci_control_port_by_index() - function to control a CCI port by port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @port: port index previously retrieved with cci_ace_get_port()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @enable: if true enables the port, if false disables it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * -ENODEV on port index out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * -EPERM if operation carried out on an ACE PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int notrace __cci_control_port_by_index(u32 port, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * CCI control for ports connected to CPUS is extremely fragile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * and must be made to go through a specific and controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * interface (ie cci_disable_port_by_cpu(); control by general purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * indexing is therefore disabled for ACE ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ports[port].type == ACE_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cci_port_control(port, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct of_device_id arm_cci_ctrl_if_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {.compatible = "arm,cci-400-ctrl-if", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int cci_probe_ports(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct cci_nb_ports const *cci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret, i, nb_ace = 0, nb_ace_lite = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct device_node *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const char *match_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bool is_ace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cci_config = of_match_node(arm_cci_matches, np)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!cci_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ports = kcalloc(nb_cci_ports, sizeof(*ports), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) for_each_available_child_of_node(np, cp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!of_match_node(arm_cci_ctrl_if_matches, cp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) i = nb_ace + nb_ace_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (i >= nb_cci_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (of_property_read_string(cp, "interface-type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &match_str)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) WARN(1, "node %pOF missing interface-type property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) is_ace = strcmp(match_str, "ace") == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!is_ace && strcmp(match_str, "ace-lite")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) WARN(1, "node %pOF containing invalid interface-type property, skipping it\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = of_address_to_resource(cp, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ports[i].base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ports[i].phys = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret || !ports[i].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WARN(1, "unable to ioremap CCI port %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (is_ace) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (WARN_ON(nb_ace >= cci_config->nb_ace))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ports[i].type = ACE_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ++nb_ace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ports[i].type = ACE_LITE_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ++nb_ace_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ports[i].dn = cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * If there is no CCI port that is under kernel control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * return early and report probe status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!nb_ace && !nb_ace_lite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* initialize a stashed array of ACE ports to speed-up look-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cci_ace_init_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Multi-cluster systems may need this data when non-coherent, during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * cluster power-up/power-down. Make sure it reaches main memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) sync_cache_w(&cci_ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sync_cache_w(&cci_ctrl_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) sync_cache_w(&ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) sync_cache_w(&cpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pr_info("ARM CCI driver probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #else /* !CONFIG_ARM_CCI400_PORT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline int cci_probe_ports(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #endif /* CONFIG_ARM_CCI400_PORT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int cci_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) np = of_find_matching_node(NULL, arm_cci_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cci_ctrl_base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cci_ctrl_phys = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret || !cci_ctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) WARN(1, "unable to ioremap CCI ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return cci_probe_ports(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int cci_init_status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static DEFINE_MUTEX(cci_probing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int cci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (cci_init_status != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return cci_init_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_lock(&cci_probing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (cci_init_status == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cci_init_status = cci_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mutex_unlock(&cci_probing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return cci_init_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * To sort out early init calls ordering a helper function is provided to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * check if the CCI driver has beed initialized. Function check if the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * has been initialized, if not it calls the init function that probes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * the driver and updates the return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bool cci_probed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return cci_init() == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) EXPORT_SYMBOL_GPL(cci_probed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) early_initcall(cci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) core_initcall(cci_platform_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_DESCRIPTION("ARM CCI support");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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