Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) *  Realtek Bluetooth USB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) *  This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) *  it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) *  the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) *  (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) *  This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) *  but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) *  GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) *  You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) *  along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /***********************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) ** Realtek - For coexistence **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define BTRTL_HCIUSB    0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BTRTL_HCIUART   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define BTRTL_HCI_IF    BTRTL_HCIUSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TRUE                1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define FALSE               0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CONNECT_PORT        30001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CONNECT_PORT_WIFI   30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define invite_req          "INVITE_REQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define invite_rsp          "INVITE_RSP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define attend_req          "ATTEND_REQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define attend_ack          "ATTEND_ACK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define wifi_leave          "WIFI_LEAVE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define leave_ack           "LEAVE_ACK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define bt_leave            "BT_LEAVE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HCI_OP_PERIODIC_INQ								0x0403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HCI_EV_LE_META			                        0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HCI_EV_LE_CONN_COMPLETE		                    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HCI_EV_LE_CONN_UPDATE_COMPLETE	                0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HCI_EV_LE_ENHANCED_CONN_COMPLETE    0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) //vendor cmd to fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HCI_VENDOR_ENABLE_PROFILE_REPORT_COMMAND        0xfc18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HCI_VENDOR_SET_PROFILE_REPORT_COMMAND           0xfc19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HCI_VENDOR_MAILBOX_CMD                          0xfc8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HCI_VENDOR_SET_BITPOOL				0xfc51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) //subcmd to fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HCI_VENDOR_SUB_CMD_WIFI_CHANNEL_AND_BANDWIDTH_CMD   0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HCI_VENDOR_SUB_CMD_WIFI_FORCE_TX_POWER_CMD          0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HCI_VENDOR_SUB_CMD_BT_ENABLE_IGNORE_WLAN_ACT_CMD    0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HCI_VENDOR_SUB_CMD_BT_REPORT_CONN_SCO_INQ_INFO      0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_STATUS_INFO       0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HCI_VENDOR_SUB_CMD_BT_AUTO_REPORT_ENABLE            0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HCI_VENDOR_SUB_CMD_BT_SET_TXRETRY_REPORT_PARAM      0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HCI_VENDOR_SUB_CMD_BT_SET_PTATABLE                  0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HCI_VENDOR_SUB_CMD_SET_BT_PSD_MODE                  0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HCI_VENDOR_SUB_CMD_SET_BT_LNA_CONSTRAINT            0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_L                    0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_M                    0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HCI_VENDOR_SUB_CMD_GET_AFH_MAP_H                    0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HCI_VENDOR_SUB_CMD_RD_REG_REQ                       0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HCI_VENDOR_SUB_CMD_WR_REG_REQ                       0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HCI_EV_VENDOR_SPECIFIC      0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) //sub event from fw start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HCI_VENDOR_PTA_REPORT_EVENT         0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HCI_VENDOR_PTA_AUTO_REPORT_EVENT    0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) //vendor cmd to wifi driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HCI_GRP_VENDOR_SPECIFIC             (0x3f << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HCI_OP_HCI_EXTENSION_VERSION_NOTIFY (0x0100 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HCI_OP_BT_OPERATION_NOTIFY          (0x0102 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HCI_OP_HCI_BT_INFO_NOTIFY           (0x0106 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HCI_OP_HCI_BT_COEX_NOTIFY           (0x0107 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HCI_OP_HCI_BT_PATCH_VER_NOTIFY      (0x0108 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HCI_OP_HCI_BT_AFH_MAP_NOTIFY        (0x0109 | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HCI_OP_HCI_BT_REGISTER_VALUE_NOTIFY (0x010a | HCI_GRP_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) //bt info reason to wifi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HOST_RESPONSE                   0	//Host response when receive the BT Info Control Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define POLLING_RESPONSE                1	//The BT Info response for polling by BT firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AUTO_REPORT                     2	//BT auto report by BT firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define STACK_REPORT_WHILE_DEVICE_D2    3	//Stack report when BT firmware is under power save state(ex:D2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) // vendor event from wifi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define RTK_HS_EXTENSION_EVENT_WIFI_SCAN            0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define RTK_HS_EXTENSION_EVENT_RADIO_STATUS_NOTIFY  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RTK_HS_EXTENSION_EVENT_HCI_BT_INFO_CONTROL  0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RTK_HS_EXTENSION_EVENT_HCI_BT_COEX_CONTROL  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) //op code from wifi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BT_PATCH_VERSION_QUERY      0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IGNORE_WLAN_ACTIVE_CONTROL  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LNA_CONSTRAIN_CONTROL       0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BT_POWER_DECREASE_CONTROL   0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BT_PSD_MODE_CONTROL         0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WIFI_BW_CHNL_NOTIFY         0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QUERY_BT_AFH_MAP            0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BT_REGISTER_ACCESS          0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) //bt operation to notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BT_OPCODE_NONE                  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BT_OPCODE_INQUIRY_START         1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BT_OPCODE_INQUIRY_END           2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BT_OPCODE_PAGE_START            3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BT_OPCODE_PAGE_SUCCESS_END      4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BT_OPCODE_PAGE_UNSUCCESS_END    5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BT_OPCODE_PAIR_START            6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BT_OPCODE_PAIR_END              7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BT_OPCODE_ENABLE_BT             8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BT_OPCODE_DISABLE_BT            9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HCI_EXTENSION_VERSION           0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HCI_CMD_PREAMBLE_SIZE           3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PAN_PACKET_COUNT                5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STREAM_TO_UINT16(u16, p) {u16 = ((uint16_t)(*(p)) + (((uint16_t)(*((p) + 1))) << 8)); (p) += 2;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UINT16_TO_STREAM(p, u16) {*(p)++ = (uint8_t)(u16); *(p)++ = (uint8_t)((u16) >> 8);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PSM_SDP     0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PSM_RFCOMM  0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PSM_PAN     0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PSM_HID     0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PSM_HID_INT 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PSM_AVCTP   0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PSM_AVDTP   0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PSM_FTP     0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PSM_BIP     0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PSM_OPP     0x1015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) //--add more if needed--//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	profile_sco = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	profile_hid = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	profile_a2dp = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	profile_pan = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	profile_hid_interval = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	profile_hogp = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	profile_voice = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	profile_sink = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	profile_max = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define A2DP_SIGNAL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define A2DP_MEDIA	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) //profile info data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	uint16_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	uint16_t psm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	uint16_t dcid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	uint16_t scid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	uint8_t profile_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } rtk_prof_info, *prtk_prof_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) //profile info for each connection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) typedef struct rtl_hci_conn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	uint16_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	uint8_t type;		// 0:l2cap, 1:sco/esco, 2:le
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	uint8_t profile_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int8_t profile_refcount[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } rtk_conn_prof, *prtk_conn_prof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct rtl_btinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u8 data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RTL_BTINFO_LEN	(sizeof(struct rtl_btinfo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * 	uint8_t cmd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * 	uint8_t cmd_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * 	uint8_t link_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * 	uint8_t retry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * 	uint8_t rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * 	uint8_t mailbox_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * 	uint16_t acl_throughput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * } hci_linkstatus_report; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } hci_mailbox_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct rtl_btinfo_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	uint8_t polling_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	uint8_t polling_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	uint8_t autoreport_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* RTB_SOFTWARE_MAILBOX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MAX_LEN_OF_HCI_EV	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define NUM_RTL_HCI_EV		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct rtl_hci_ev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	__u8 data[MAX_LEN_OF_HCI_EV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	__u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define L2_MAX_SUBSEC_LEN	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define L2_MAX_PKTS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct rtl_l2_buff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	__u8 data[L2_MAX_SUBSEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	__u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	__u16 out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct rtl_coex_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct list_head conn_hash;	//hash for connections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct list_head profile_list;	//hash for profile info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct socket *udpsock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct sockaddr_in addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct sockaddr_in wifi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct timer_list polling_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct timer_list a2dp_count_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct timer_list pan_count_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct timer_list hogp_count_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct workqueue_struct *sock_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct delayed_work sock_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct workqueue_struct *fw_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct delayed_work fw_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct delayed_work l2_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct sock *sk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	spinlock_t spin_lock_sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	spinlock_t spin_lock_profile;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	uint32_t a2dp_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	uint32_t pan_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	uint32_t hogp_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	uint32_t voice_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	uint8_t profile_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	uint8_t profile_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int8_t profile_refcount[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	uint8_t ispairing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	uint8_t isinquirying;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	uint8_t ispaging;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	uint8_t wifi_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	uint8_t autoreport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	uint8_t polling_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	uint8_t polling_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	uint8_t piconet_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	uint8_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	uint8_t afh_map[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	uint16_t hci_reversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	uint16_t lmp_subversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef RTB_SOFTWARE_MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	uint8_t wifi_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	uint8_t sock_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned long cmd_last_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* hci ev buff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct list_head ev_used_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct list_head ev_free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	spinlock_t rxlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	__u8 pkt_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	__u16 expect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	__u8 *tbuff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	__u16 elen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	__u8 back_buff[HCI_MAX_EVENT_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* l2cap rx buff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct list_head l2_used_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct list_head l2_free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* buff addr and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	spinlock_t buff_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	unsigned long pages_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	unsigned long buff_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define RTL_COEX_RUNNING	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sbc_frame_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	uint8_t syncword:8;		/* Sync word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	uint8_t subbands:1;		/* Subbands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	uint8_t allocation_method:1;	/* Allocation method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	uint8_t channel_mode:2;		/* Channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	uint8_t blocks:2;		/* Blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	uint8_t sampling_frequency:2;	/* Sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	uint8_t bitpool:8;		/* Bitpool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	uint8_t crc_check:8;		/* CRC check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* NOTE: The code is copied from pa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * only the bit field in 8-bit is affected by endian, not the 16-bit or 32-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * why?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rtp_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	unsigned cc:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	unsigned x:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	unsigned p:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	unsigned v:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned pt:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	unsigned m:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	uint16_t sequence_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	uint32_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	uint32_t ssrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	uint32_t csrc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct sbc_frame_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	uint8_t syncword:8;		/* Sync word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	uint8_t sampling_frequency:2;	/* Sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	uint8_t blocks:2;		/* Blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	uint8_t channel_mode:2;		/* Channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	uint8_t allocation_method:1;	/* Allocation method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	uint8_t subbands:1;		/* Subbands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	uint8_t bitpool:8;		/* Bitpool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	uint8_t crc_check:8;		/* CRC check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct rtp_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	unsigned v:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	unsigned p:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	unsigned x:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	unsigned cc:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	unsigned m:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	unsigned pt:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	uint16_t sequence_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	uint32_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	uint32_t ssrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	uint32_t csrc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void rtk_btcoex_parse_event(uint8_t *buffer, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void rtk_btcoex_parse_cmd(uint8_t *buffer, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void rtk_btcoex_parse_l2cap_data_tx(uint8_t *buffer, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void rtk_btcoex_parse_l2cap_data_rx(uint8_t *buffer, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void rtk_btcoex_open(struct hci_dev *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void rtk_btcoex_close(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void rtk_btcoex_probe(struct hci_dev *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void rtk_btcoex_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void rtk_btcoex_exit(void);