^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Bluetooth HCI UART driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000-2001 Qualcomm Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2002-2003 Maxim Krasnyansky <maxk@qualcomm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004-2005 Marcel Holtmann <marcel@holtmann.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef N_HCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define N_HCI 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HCIUARTSETPROTO _IOW('U', 200, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HCIUARTGETPROTO _IOR('U', 201, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HCIUARTGETDEVICE _IOR('U', 202, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HCIUARTSETFLAGS _IOW('U', 203, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HCIUARTGETFLAGS _IOR('U', 204, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* UART protocols */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HCI_UART_MAX_PROTO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HCI_UART_H4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HCI_UART_BCSP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HCI_UART_3WIRE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HCI_UART_H4DS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HCI_UART_LL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HCI_UART_ATH3K 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HCI_UART_INTEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HCI_UART_BCM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HCI_UART_QCA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HCI_UART_AG6XX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HCI_UART_NOKIA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HCI_UART_MRVL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HCI_UART_RAW_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HCI_UART_RESET_ON_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HCI_UART_CREATE_AMP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HCI_UART_INIT_PENDING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HCI_UART_EXT_CONFIG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HCI_UART_VND_DETECT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct hci_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct serdev_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct hci_uart_proto {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int manufacturer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int init_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int oper_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int (*open)(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int (*close)(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int (*flush)(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int (*setup)(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int (*set_baudrate)(struct hci_uart *hu, unsigned int speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int (*recv)(struct hci_uart *hu, const void *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int (*enqueue)(struct hci_uart *hu, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct sk_buff *(*dequeue)(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct hci_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct serdev_device *serdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long hdev_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct work_struct init_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct work_struct write_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const struct hci_uart_proto *proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct percpu_rw_semaphore proto_lock; /* Stop work for proto close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int init_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int oper_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* HCI_UART proto flag bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HCI_UART_PROTO_SET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HCI_UART_REGISTERED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HCI_UART_PROTO_READY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* TX states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HCI_UART_SENDING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HCI_UART_TX_WAKEUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int hci_uart_register_proto(const struct hci_uart_proto *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int hci_uart_unregister_proto(const struct hci_uart_proto *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int hci_uart_register_device(struct hci_uart *hu, const struct hci_uart_proto *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void hci_uart_unregister_device(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int hci_uart_tx_wakeup(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int hci_uart_wait_until_sent(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int hci_uart_init_ready(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void hci_uart_init_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool hci_uart_has_flow_control(struct hci_uart *hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void hci_uart_set_flow_control(struct hci_uart *hu, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int oper_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_BT_HCIUART_H4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int h4_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int h4_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct h4_recv_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 type; /* Packet type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 hlen; /* Header length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 loff; /* Data length offset in header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 lsize; /* Data length field size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 maxlen; /* Max overall packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int (*recv)(struct hci_dev *hdev, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define H4_RECV_ACL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .type = HCI_ACLDATA_PKT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .hlen = HCI_ACL_HDR_SIZE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .loff = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .lsize = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .maxlen = HCI_MAX_FRAME_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define H4_RECV_SCO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .type = HCI_SCODATA_PKT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .hlen = HCI_SCO_HDR_SIZE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .loff = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .lsize = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .maxlen = HCI_MAX_SCO_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define H4_RECV_EVENT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .type = HCI_EVENT_PKT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hlen = HCI_EVENT_HDR_SIZE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .loff = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .lsize = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .maxlen = HCI_MAX_EVENT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define H4_RECV_ISO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .type = HCI_ISODATA_PKT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .hlen = HCI_ISO_HDR_SIZE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .loff = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .lsize = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .maxlen = HCI_MAX_FRAME_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct sk_buff *h4_recv_buf(struct hci_dev *hdev, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const unsigned char *buffer, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct h4_recv_pkt *pkts, int pkts_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_BT_HCIUART_BCSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int bcsp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int bcsp_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_BT_HCIUART_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ll_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ll_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef CONFIG_BT_HCIUART_ATH3K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ath_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ath_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_BT_HCIUART_3WIRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int h5_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int h5_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef CONFIG_BT_HCIUART_INTEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int intel_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int intel_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_BT_HCIUART_BCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int bcm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int bcm_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_BT_HCIUART_QCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int qca_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int qca_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_BT_HCIUART_AG6XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ag6xx_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ag6xx_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_BT_HCIUART_MRVL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int mrvl_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int mrvl_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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