^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros Communication Bluetooth HCIATH3K UART protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * HCIATH3K (HCI Atheros AR300x Protocol) is a Atheros Communication's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * power management protocol extension to H4 to support AR300x Bluetooth Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2009-2010 Atheros Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Acknowledgements:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is based on hci_h4.c, which was written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * by Maxim Krasnyansky and Marcel Holtmann.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <net/bluetooth/bluetooth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "hci_uart.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct ath_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct hci_uart *hu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int cur_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sk_buff *rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct sk_buff_head txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct work_struct ctxtsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OP_WRITE_TAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define INDEX_BDADDR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct ath_vendor_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __le16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __u8 data[251];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int ath_wakeup_ar3k(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int status = tty->driver->ops->tiocmget(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (status & TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Clear RTS first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) tty->driver->ops->tiocmget(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tty->driver->ops->tiocmset(tty, 0x00, TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Set RTS, wake up board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tty->driver->ops->tiocmget(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tty->driver->ops->tiocmset(tty, TIOCM_RTS, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) status = tty->driver->ops->tiocmget(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void ath_hci_uart_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct ath_struct *ath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct hci_uart *hu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ath = container_of(work, struct ath_struct, ctxtsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) hu = ath->hu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tty = hu->tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* verify and wake up controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ath->cur_sleep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) status = ath_wakeup_ar3k(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!(status & TIOCM_CTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Ready to send Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clear_bit(HCI_UART_SENDING, &hu->tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hci_uart_tx_wakeup(hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int ath_open(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ath_struct *ath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!hci_uart_has_flow_control(hu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ath = kzalloc(sizeof(*ath), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!ath)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) skb_queue_head_init(&ath->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hu->priv = ath;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ath->hu = hu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) INIT_WORK(&ath->ctxtsw, ath_hci_uart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ath_close(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ath_struct *ath = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) skb_queue_purge(&ath->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) kfree_skb(ath->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cancel_work_sync(&ath->ctxtsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) hu->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) kfree(ath);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int ath_flush(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ath_struct *ath = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) skb_queue_purge(&ath->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ath_vendor_cmd(struct hci_dev *hdev, uint8_t opcode, uint16_t index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const void *data, size_t dlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct ath_vendor_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (dlen > sizeof(cmd.data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cmd.opcode = opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cmd.index = cpu_to_le16(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cmd.len = dlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) memcpy(cmd.data, data, dlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) skb = __hci_cmd_sync(hdev, 0xfc0b, dlen + 4, &cmd, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (IS_ERR(skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int ath_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ath_vendor_cmd(hdev, OP_WRITE_TAG, INDEX_BDADDR, bdaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sizeof(*bdaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ath_setup(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) hu->hdev->set_bdaddr = ath_set_bdaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct h4_recv_pkt ath_recv_pkts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { H4_RECV_ACL, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { H4_RECV_SCO, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { H4_RECV_EVENT, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int ath_recv(struct hci_uart *hu, const void *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ath_struct *ath = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ath->rx_skb = h4_recv_buf(hu->hdev, ath->rx_skb, data, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ath_recv_pkts, ARRAY_SIZE(ath_recv_pkts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ERR(ath->rx_skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int err = PTR_ERR(ath->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ath->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HCI_OP_ATH_SLEEP 0xFC04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int ath_enqueue(struct hci_uart *hu, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ath_struct *ath = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (hci_skb_pkt_type(skb) == HCI_SCODATA_PKT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Update power management enable flag with parameters of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * HCI sleep enable vendor specific HCI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (hci_skb_pkt_type(skb) == HCI_COMMAND_PKT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct hci_command_hdr *hdr = (void *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (__le16_to_cpu(hdr->opcode) == HCI_OP_ATH_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ath->cur_sleep = skb->data[HCI_COMMAND_HDR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) BT_DBG("hu %p skb %p", hu, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Prepend skb with frame type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) skb_queue_tail(&ath->txq, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) set_bit(HCI_UART_SENDING, &hu->tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) schedule_work(&ath->ctxtsw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct sk_buff *ath_dequeue(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ath_struct *ath = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return skb_dequeue(&ath->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct hci_uart_proto athp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .id = HCI_UART_ATH3K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "ATH3K",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .manufacturer = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .open = ath_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .close = ath_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .flush = ath_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .setup = ath_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .recv = ath_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .enqueue = ath_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .dequeue = ath_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int __init ath_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return hci_uart_register_proto(&athp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int __exit ath_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return hci_uart_unregister_proto(&athp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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