^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Bluetooth HCI UART driver for Intel/AG6xx devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <net/bluetooth/bluetooth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hci_uart.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "btintel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct ag6xx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct sk_buff *rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct sk_buff_head txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct pbn_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __le32 plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int ag6xx_open(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ag6xx_data *ag6xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ag6xx = kzalloc(sizeof(*ag6xx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (!ag6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) skb_queue_head_init(&ag6xx->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) hu->priv = ag6xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int ag6xx_close(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct ag6xx_data *ag6xx = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) skb_queue_purge(&ag6xx->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) kfree_skb(ag6xx->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) kfree(ag6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) hu->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int ag6xx_flush(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ag6xx_data *ag6xx = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BT_DBG("hu %p", hu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) skb_queue_purge(&ag6xx->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct sk_buff *ag6xx_dequeue(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct ag6xx_data *ag6xx = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) skb = skb_dequeue(&ag6xx->txq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Prepend skb with frame type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int ag6xx_enqueue(struct hci_uart *hu, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ag6xx_data *ag6xx = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) skb_queue_tail(&ag6xx->txq, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct h4_recv_pkt ag6xx_recv_pkts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { H4_RECV_ACL, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { H4_RECV_SCO, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { H4_RECV_EVENT, .recv = hci_recv_frame },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ag6xx_recv(struct hci_uart *hu, const void *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ag6xx_data *ag6xx = hu->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EUNATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ag6xx->rx_skb = h4_recv_buf(hu->hdev, ag6xx->rx_skb, data, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ag6xx_recv_pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ARRAY_SIZE(ag6xx_recv_pkts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(ag6xx->rx_skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int err = PTR_ERR(ag6xx->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ag6xx->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int intel_mem_write(struct hci_dev *hdev, u32 addr, u32 plen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Can write a maximum of 247 bytes per HCI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * HCI cmd Header (3), Intel mem write header (6), data (247).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (plen > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 cmd_param[253], fragment_len = (plen > 247) ? 247 : plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __le32 leaddr = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) memcpy(cmd_param, &leaddr, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cmd_param[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cmd_param[5] = fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) memcpy(cmd_param + 6, data, fragment_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) skb = __hci_cmd_sync(hdev, 0xfc8e, fragment_len + 6, cmd_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (IS_ERR(skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) plen -= fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data += fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) addr += fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int ag6xx_setup(struct hci_uart *hu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct hci_dev *hdev = hu->hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct intel_version ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const u8 *fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) char fwname[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool patched = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hu->hdev->set_diag = btintel_set_diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) hu->hdev->set_bdaddr = btintel_set_bdaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) err = btintel_enter_mfg(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = btintel_read_version(hdev, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) btintel_version_info(hdev, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* The hardware platform number has a fixed value of 0x37 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * for now only accept this single value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ver.hw_platform != 0x37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bt_dev_err(hdev, "Unsupported Intel hardware platform: 0x%X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ver.hw_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Only the hardware variant iBT 2.1 (AG6XX) is supported by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * firmware setup method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ver.hw_variant != 0x0a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bt_dev_err(hdev, "Unsupported Intel hardware variant: 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ver.hw_variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) snprintf(fwname, sizeof(fwname), "intel/ibt-hw-%x.%x.bddata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ver.hw_platform, ver.hw_variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err = request_firmware(&fw, fwname, &hdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bt_dev_err(hdev, "Failed to open Intel bddata file: %s (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) fw_ptr = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bt_dev_info(hdev, "Applying bddata (%s)", fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) skb = __hci_cmd_sync_ev(hdev, 0xfc2f, fw->size, fw->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) HCI_EV_CMD_STATUS, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bt_dev_err(hdev, "Applying bddata failed (%ld)", PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) patch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* If there is no applied patch, fw_patch_num is always 0x00. In other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * cases, current firmware is already patched. No need to patch it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ver.fw_patch_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bt_dev_info(hdev, "Device is already patched. patch num: %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ver.fw_patch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) patched = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) snprintf(fwname, sizeof(fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "intel/ibt-hw-%x.%x.%x-fw-%x.%x.%x.%x.%x.pbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ver.hw_platform, ver.hw_variant, ver.hw_revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ver.fw_variant, ver.fw_revision, ver.fw_build_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ver.fw_build_ww, ver.fw_build_yy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) err = request_firmware(&fw, fwname, &hdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bt_dev_err(hdev, "Failed to open Intel patch file: %s(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fwname, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) fw_ptr = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bt_dev_info(hdev, "Patching firmware file (%s)", fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* PBN patch file contains a list of binary patches to be applied on top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * of the embedded firmware. Each patch entry header contains the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * address and patch size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Patch entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * | addr(le) | patch_len(le) | patch_data |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * | 4 Bytes | 4 Bytes | n Bytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * PBN file is terminated by a patch entry whose address is 0xffffffff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) while (fw->size > fw_ptr - fw->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct pbn_entry *pbn = (void *)fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 addr, plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (pbn->addr == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bt_dev_info(hdev, "Patching complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) patched = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) addr = le32_to_cpu(pbn->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) plen = le32_to_cpu(pbn->plen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (fw->data + fw->size <= pbn->data + plen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bt_dev_info(hdev, "Invalid patch len (%d)", plen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bt_dev_info(hdev, "Patching %td/%zu", (fw_ptr - fw->data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err = intel_mem_write(hdev, addr, plen, pbn->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bt_dev_err(hdev, "Patching failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) fw_ptr = pbn->data + plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Exit manufacturing mode and reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err = btintel_exit_mfg(hdev, true, patched);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Set the event mask for Intel specific vendor events. This enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * a few extra events that are useful during general operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) btintel_set_event_mask_mfg(hdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) btintel_check_bdaddr(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct hci_uart_proto ag6xx_proto = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .id = HCI_UART_AG6XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .name = "AG6XX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .manufacturer = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .open = ag6xx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .close = ag6xx_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .flush = ag6xx_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .setup = ag6xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .recv = ag6xx_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .enqueue = ag6xx_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .dequeue = ag6xx_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int __init ag6xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return hci_uart_register_proto(&ag6xx_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int __exit ag6xx_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return hci_uart_unregister_proto(&ag6xx_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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