^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bluetooth supports for Qualcomm Atheros ROME chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define EDL_PATCH_CMD_OPCODE (0xFC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define EDL_NVM_ACCESS_OPCODE (0xFC0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define EDL_WRITE_BD_ADDR_OPCODE (0xFC14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define EDL_PATCH_CMD_LEN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define EDL_PATCH_VER_REQ_CMD (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EDL_PATCH_TLV_REQ_CMD (0x1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EDL_NVM_ACCESS_SET_REQ_CMD (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_SIZE_PER_TLV_SEGMENT (243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QCA_PRE_SHUTDOWN_CMD (0xFC08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define QCA_DISABLE_LOGGING (0xFC17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EDL_CMD_REQ_RES_EVT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EDL_PATCH_VER_RES_EVT (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDL_APP_VER_RES_EVT (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDL_TVL_DNLD_RES_EVT (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EDL_CMD_EXE_STATUS_EVT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EDL_SET_BAUDRATE_RSP_EVT (0x92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EDL_NVM_ACCESS_CODE_EVT (0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QCA_DISABLE_LOGGING_SUB_OP (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EDL_TAG_ID_HCI (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EDL_TAG_ID_DEEP_SLEEP (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QCA_WCN3990_POWERON_PULSE 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QCA_WCN3990_POWEROFF_PULSE 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QCA_HCI_CC_OPCODE 0xFC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QCA_HCI_CC_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum qca_baudrate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) QCA_BAUDRATE_115200 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) QCA_BAUDRATE_57600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) QCA_BAUDRATE_38400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) QCA_BAUDRATE_19200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) QCA_BAUDRATE_9600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) QCA_BAUDRATE_230400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) QCA_BAUDRATE_250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) QCA_BAUDRATE_460800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) QCA_BAUDRATE_500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) QCA_BAUDRATE_720000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) QCA_BAUDRATE_921600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) QCA_BAUDRATE_1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) QCA_BAUDRATE_1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) QCA_BAUDRATE_2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) QCA_BAUDRATE_3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) QCA_BAUDRATE_4000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) QCA_BAUDRATE_1600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) QCA_BAUDRATE_3200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) QCA_BAUDRATE_3500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) QCA_BAUDRATE_AUTO = 0xFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) QCA_BAUDRATE_RESERVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum qca_tlv_dnld_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) QCA_SKIP_EVT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) QCA_SKIP_EVT_VSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) QCA_SKIP_EVT_CC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) QCA_SKIP_EVT_VSE_CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum qca_tlv_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) TLV_TYPE_PATCH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TLV_TYPE_NVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct qca_fw_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) char fwname[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) uint8_t user_baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum qca_tlv_dnld_mode dnld_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum qca_tlv_dnld_mode dnld_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct edl_event_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u8 cresp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u8 rtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct qca_btsoc_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le32 product_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __le16 patch_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le16 rom_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __le32 soc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct tlv_seg_resp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u8 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct tlv_type_patch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le32 total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __le32 data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u8 format_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __u8 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u8 download_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __le16 product_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __le16 rom_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le16 patch_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __le16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __le32 entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct tlv_type_nvm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __le16 tag_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le16 tag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le32 reserve1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le32 reserve2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tlv_type_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __le32 type_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum qca_btsoc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) QCA_INVALID = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) QCA_AR3002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) QCA_ROME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) QCA_WCN3990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) QCA_WCN3998,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) QCA_WCN3991,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) QCA_QCA6390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #if IS_ENABLED(CONFIG_BT_QCA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum qca_btsoc_type soc_type, u32 soc_ver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int qca_read_soc_version(struct hci_dev *hdev, u32 *soc_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum qca_btsoc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return soc_type == QCA_WCN3990 || soc_type == QCA_WCN3991 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) soc_type == QCA_WCN3998;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum qca_btsoc_type soc_type, u32 soc_ver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const char *firmware_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline int qca_read_soc_version(struct hci_dev *hdev, u32 *soc_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum qca_btsoc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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