^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bluetooth supports for Qualcomm Atheros chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <net/bluetooth/bluetooth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "btqca.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VERSION "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int qca_read_soc_version(struct hci_dev *hdev, u32 *soc_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct edl_event_hdr *edl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct qca_btsoc_version *ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 event_type = HCI_EV_VENDOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 rlen = sizeof(*edl) + sizeof(*ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 rtype = EDL_APP_VER_RES_EVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bt_dev_dbg(hdev, "QCA Version Request");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Unlike other SoC's sending version command response as payload to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * VSE event. WCN3991 sends version command response as a payload to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * command complete event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (soc_type >= QCA_WCN3991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) event_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) rlen += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) rtype = EDL_PATCH_VER_REQ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cmd = EDL_PATCH_VER_REQ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, EDL_PATCH_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &cmd, event_type, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bt_dev_err(hdev, "Reading QCA version information failed (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (skb->len != rlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bt_dev_err(hdev, "QCA Version size mismatch len %d", skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) edl = (struct edl_event_hdr *)(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!edl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bt_dev_err(hdev, "QCA TLV with no header");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (edl->cresp != EDL_CMD_REQ_RES_EVT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) edl->rtype != rtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bt_dev_err(hdev, "QCA Wrong packet received %d %d", edl->cresp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) edl->rtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (soc_type >= QCA_WCN3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) memmove(&edl->data, &edl->data[1], sizeof(*ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ver = (struct qca_btsoc_version *)(edl->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bt_dev_info(hdev, "QCA Product ID :0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) le32_to_cpu(ver->product_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bt_dev_info(hdev, "QCA SOC Version :0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) le32_to_cpu(ver->soc_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bt_dev_info(hdev, "QCA ROM Version :0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) le16_to_cpu(ver->rom_ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bt_dev_info(hdev, "QCA Patch Version:0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) le16_to_cpu(ver->patch_ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* QCA chipset version can be decided by patch and SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * version, combination with upper 2 bytes from SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * and lower 2 bytes from patch will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *soc_version = (le32_to_cpu(ver->soc_id) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (le16_to_cpu(ver->rom_ver) & 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (*soc_version == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bt_dev_err(hdev, "QCA Failed to get version (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL_GPL(qca_read_soc_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int qca_send_reset(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bt_dev_dbg(hdev, "QCA HCI_RESET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bt_dev_err(hdev, "QCA Reset failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bt_dev_dbg(hdev, "QCA pre shutdown cmd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) skb = __hci_cmd_sync_ev(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) NULL, HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bt_dev_err(hdev, "QCA preshutdown_cmd failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(qca_send_pre_shutdown_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void qca_tlv_check_data(struct qca_fw_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 *fw_data, enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 type_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 tag_id, tag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int idx, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct tlv_type_hdr *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct tlv_type_patch *tlv_patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct tlv_type_nvm *tlv_nvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint8_t nvm_baud_rate = config->user_baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tlv = (struct tlv_type_hdr *)fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) type_len = le32_to_cpu(tlv->type_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) length = (type_len >> 8) & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) BT_DBG("TLV Type\t\t : 0x%x", type_len & 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BT_DBG("Length\t\t : %d bytes", length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) config->dnld_mode = QCA_SKIP_EVT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) config->dnld_type = QCA_SKIP_EVT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (config->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case TLV_TYPE_PATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tlv_patch = (struct tlv_type_patch *)tlv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* For Rome version 1.1 to 3.1, all segment commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * are acked by a vendor specific event (VSE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * For Rome >= 3.2, the download mode field indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * if VSE is skipped by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * In case VSE is skipped, only the last segment is acked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) config->dnld_mode = tlv_patch->download_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) config->dnld_type = config->dnld_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BT_DBG("Total Length : %d bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) le32_to_cpu(tlv_patch->total_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BT_DBG("Patch Data Length : %d bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) le32_to_cpu(tlv_patch->data_length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BT_DBG("Signing Format Version : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tlv_patch->format_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BT_DBG("Signature Algorithm : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tlv_patch->signature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BT_DBG("Download mode : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tlv_patch->download_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BT_DBG("Reserved : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tlv_patch->reserved1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BT_DBG("Product ID : 0x%04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) le16_to_cpu(tlv_patch->product_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) BT_DBG("Rom Build Version : 0x%04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) le16_to_cpu(tlv_patch->rom_build));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) BT_DBG("Patch Version : 0x%04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) le16_to_cpu(tlv_patch->patch_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) BT_DBG("Reserved : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) le16_to_cpu(tlv_patch->reserved2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BT_DBG("Patch Entry Address : 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) le32_to_cpu(tlv_patch->entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case TLV_TYPE_NVM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data = tlv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) while (idx < length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tlv_nvm = (struct tlv_type_nvm *)(data + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tag_id = le16_to_cpu(tlv_nvm->tag_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tag_len = le16_to_cpu(tlv_nvm->tag_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Update NVM tags as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (tag_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case EDL_TAG_ID_HCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* HCI transport layer parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * enabling software inband sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * onto controller side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tlv_nvm->data[0] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* UART Baud Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (soc_type >= QCA_WCN3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tlv_nvm->data[1] = nvm_baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tlv_nvm->data[2] = nvm_baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case EDL_TAG_ID_DEEP_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Sleep enable mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * enabling deep sleep feature on controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tlv_nvm->data[0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) idx += (sizeof(u16) + sizeof(u16) + 8 + tag_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BT_ERR("Unknown TLV type %d", config->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int qca_tlv_send_segment(struct hci_dev *hdev, int seg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const u8 *data, enum qca_tlv_dnld_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct edl_event_hdr *edl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct tlv_seg_resp *tlv_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 cmd[MAX_SIZE_PER_TLV_SEGMENT + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 event_type = HCI_EV_VENDOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 rlen = (sizeof(*edl) + sizeof(*tlv_resp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 rtype = EDL_TVL_DNLD_RES_EVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cmd[0] = EDL_PATCH_TLV_REQ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cmd[1] = seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) memcpy(cmd + 2, data, seg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (mode == QCA_SKIP_EVT_VSE_CC || mode == QCA_SKIP_EVT_VSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return __hci_cmd_send(hdev, EDL_PATCH_CMD_OPCODE, seg_size + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Unlike other SoC's sending version command response as payload to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * VSE event. WCN3991 sends version command response as a payload to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * command complete event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (soc_type >= QCA_WCN3991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) event_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rlen = sizeof(*edl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rtype = EDL_PATCH_TLV_REQ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, seg_size + 2, cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) event_type, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bt_dev_err(hdev, "QCA Failed to send TLV segment (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (skb->len != rlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bt_dev_err(hdev, "QCA TLV response size mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) edl = (struct edl_event_hdr *)(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!edl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bt_dev_err(hdev, "TLV with no header");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (edl->cresp != EDL_CMD_REQ_RES_EVT || edl->rtype != rtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bt_dev_err(hdev, "QCA TLV with error stat 0x%x rtype 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) edl->cresp, edl->rtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (soc_type >= QCA_WCN3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) tlv_resp = (struct tlv_seg_resp *)(edl->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (tlv_resp->result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bt_dev_err(hdev, "QCA TLV with error stat 0x%x rtype 0x%x (0x%x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) edl->cresp, edl->rtype, tlv_resp->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int qca_inject_cmd_complete_event(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct hci_event_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct hci_ev_cmd_complete *evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) skb = bt_skb_alloc(sizeof(*hdr) + sizeof(*evt) + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hdr = skb_put(skb, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hdr->evt = HCI_EV_CMD_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hdr->plen = sizeof(*evt) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) evt = skb_put(skb, sizeof(*evt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) evt->ncmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) evt->opcode = cpu_to_le16(QCA_HCI_CC_OPCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) skb_put_u8(skb, QCA_HCI_CC_SUCCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hci_skb_pkt_type(skb) = HCI_EVENT_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return hci_recv_frame(hdev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int qca_download_firmware(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct qca_fw_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum qca_btsoc_type soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const u8 *segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret, size, remain, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bt_dev_info(hdev, "QCA Downloading %s", config->fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = request_firmware(&fw, config->fwname, &hdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bt_dev_err(hdev, "QCA Failed to request file: %s (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) config->fwname, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) size = fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) data = vmalloc(fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bt_dev_err(hdev, "QCA Failed to allocate memory for file: %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) config->fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) memcpy(data, fw->data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) qca_tlv_check_data(config, data, soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) segment = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) remain = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int segsize = min(MAX_SIZE_PER_TLV_SEGMENT, remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bt_dev_dbg(hdev, "Send segment %d, size %d", i++, segsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) remain -= segsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* The last segment is always acked regardless download mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!remain || segsize < MAX_SIZE_PER_TLV_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) config->dnld_mode = QCA_SKIP_EVT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = qca_tlv_send_segment(hdev, segsize, segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) config->dnld_mode, soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) segment += segsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Latest qualcomm chipsets are not sending a command complete event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * for every fw packet sent. They only respond with a vendor specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * event for the last packet. This optimization in the chip will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * decrease the BT in initialization time. Here we will inject a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * complete event to avoid a command timeout error message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (config->dnld_type == QCA_SKIP_EVT_VSE_CC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) config->dnld_type == QCA_SKIP_EVT_VSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = qca_inject_cmd_complete_event(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) vfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int qca_disable_soc_logging(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 cmd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cmd[0] = QCA_DISABLE_LOGGING_SUB_OP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cmd[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) skb = __hci_cmd_sync_ev(hdev, QCA_DISABLE_LOGGING, sizeof(cmd), cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bt_dev_err(hdev, "QCA Failed to disable soc logging(%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 cmd[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cmd[0] = EDL_NVM_ACCESS_SET_REQ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cmd[1] = 0x02; /* TAG ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cmd[2] = sizeof(bdaddr_t); /* size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) memcpy(cmd + 3, bdaddr, sizeof(bdaddr_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) skb = __hci_cmd_sync_ev(hdev, EDL_NVM_ACCESS_OPCODE, sizeof(cmd), cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) HCI_EV_VENDOR, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bt_dev_err(hdev, "QCA Change address command failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) EXPORT_SYMBOL_GPL(qca_set_bdaddr_rome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) enum qca_btsoc_type soc_type, u32 soc_ver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const char *firmware_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct qca_fw_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 rom_ver = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bt_dev_dbg(hdev, "QCA setup on UART");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) config.user_baud_rate = baudrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Download rampatch file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) config.type = TLV_TYPE_PATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (qca_is_wcn399x(soc_type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Firmware files to download are based on ROM version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * ROM version is derived from last two bytes of soc_ver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rom_ver = ((soc_ver & 0x00000f00) >> 0x04) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (soc_ver & 0x0000000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "qca/crbtfw%02x.tlv", rom_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else if (soc_type == QCA_QCA6390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rom_ver = ((soc_ver & 0x00000f00) >> 0x04) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (soc_ver & 0x0000000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "qca/htbtfw%02x.tlv", rom_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "qca/rampatch_%08x.bin", soc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err = qca_download_firmware(hdev, &config, soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) bt_dev_err(hdev, "QCA Failed to download patch (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Give the controller some time to get ready to receive the NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Download NVM configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) config.type = TLV_TYPE_NVM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (firmware_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "qca/%s", firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else if (qca_is_wcn399x(soc_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "qca/crnv%02x.bin", rom_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else if (soc_type == QCA_QCA6390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "qca/htnv%02x.bin", rom_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) snprintf(config.fwname, sizeof(config.fwname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "qca/nvm_%08x.bin", soc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err = qca_download_firmware(hdev, &config, soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bt_dev_err(hdev, "QCA Failed to download NVM (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (soc_type >= QCA_WCN3991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err = qca_disable_soc_logging(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Perform HCI reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err = qca_send_reset(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bt_dev_err(hdev, "QCA Failed to run HCI_RESET (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bt_dev_info(hdev, "QCA setup on UART is completed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) EXPORT_SYMBOL_GPL(qca_uart_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) skb = __hci_cmd_sync_ev(hdev, EDL_WRITE_BD_ADDR_OPCODE, 6, bdaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) HCI_EV_VENDOR, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) bt_dev_err(hdev, "QCA Change address cmd failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) EXPORT_SYMBOL_GPL(qca_set_bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_AUTHOR("Ben Young Tae Kim <ytkim@qca.qualcomm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_DESCRIPTION("Bluetooth support for Qualcomm Atheros family ver " VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_VERSION(VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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