^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Marvell BT-over-SDIO driver: SDIO interface related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009, Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This software file (the "File") is distributed by Marvell International
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ltd. under the terms of the GNU General Public License Version 2, June 1991
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (the "License"). You may use, redistribute and/or modify this File in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * accordance with the terms and conditions of the License, a copy of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * is available by writing to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * this warranty disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SDIO_HEADER_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* SD block size can not bigger than 64 due to buf size limit in firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* define SD block size for data Tx/Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDIO_BLOCK_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Number of blocks for firmware transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FIRMWARE_TRANSFER_NBLOCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* This is for firmware specific length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FW_EXTRA_LEN 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * SDIO_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* The number of times to try when polling for status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX_POLL_TRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Max retry number of CMD53 write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX_WRITE_IOMEM_RETRY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HOST_POWER_UP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HOST_CMD53_FIN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HIM_DISABLE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HIM_ENABLE (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UP_LD_HOST_INT_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DN_LD_HOST_INT_STATUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DN_LD_CARD_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CARD_IO_READY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FIRMWARE_READY 0xfedc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct btmrvl_plt_wake_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int irq_bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool wake_by_bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct btmrvl_sdio_card_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 host_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 host_intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 card_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 sq_read_base_addr_a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 sq_read_base_addr_a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 card_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 card_fw_status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 card_fw_status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 card_rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 card_rx_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 io_port_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 io_port_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 io_port_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool int_read_to_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 host_int_rsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 card_misc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 fw_dump_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 fw_dump_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 fw_dump_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct btmrvl_sdio_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sdio_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *helper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct btmrvl_sdio_card_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool support_pscan_win_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool supports_fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 sd_blksz_fw_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 rx_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct btmrvl_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device_node *plt_of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct btmrvl_plt_wake_cfg *plt_wake_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct btmrvl_sdio_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *helper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct btmrvl_sdio_card_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const bool support_pscan_win_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 sd_blksz_fw_dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool supports_fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Platform specific DMA alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BTSDIO_DMA_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Macros for Data Alignment : size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ALIGN_SZ(p, a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (((p) + ((a) - 1)) & ~((a) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Macros for Data Alignment : address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ALIGN_ADDR(p, a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ~(((unsigned long)(a)) - 1))
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags