^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Bluetooth support for Intel devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <net/bluetooth/bluetooth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "btintel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VERSION "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BDADDR_INTEL (&(bdaddr_t){{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RSA_HEADER_LEN 644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSS_HEADER_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ECDSA_OFFSET 644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ECDSA_HEADER_LEN 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int btintel_check_bdaddr(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct hci_rp_read_bd_addr *bda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bt_dev_err(hdev, "Reading Intel device address failed (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (skb->len != sizeof(*bda)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bt_dev_err(hdev, "Intel device address length mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bda = (struct hci_rp_read_bd_addr *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* For some Intel based controllers, the default Bluetooth device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * address 00:03:19:9E:8B:00 can be found. These controllers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * fully operational, but have the danger of duplicate addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * and that in turn can cause problems with Bluetooth operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bt_dev_err(hdev, "Found Intel default device address (%pMR)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) &bda->bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) EXPORT_SYMBOL_GPL(btintel_check_bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int btintel_enter_mfg(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const u8 param[] = { 0x01, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) EXPORT_SYMBOL_GPL(btintel_enter_mfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 param[] = { 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* The 2nd command parameter specifies the manufacturing exit method:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 0x00: Just disable the manufacturing mode (0x00).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 0x01: Disable manufacturing mode and reset with patches deactivated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0x02: Disable manufacturing mode and reset with patches activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) param[1] |= patched ? 0x02 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) EXPORT_SYMBOL_GPL(btintel_exit_mfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bt_dev_err(hdev, "Changing Intel device address failed (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL_GPL(btintel_set_bdaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int btintel_set_diag(struct hci_dev *hdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 param[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) param[0] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) param[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) param[2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) param[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) param[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) param[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (err == -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bt_dev_err(hdev, "Changing Intel diagnostic mode failed (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) btintel_set_event_mask(hdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXPORT_SYMBOL_GPL(btintel_set_diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int err, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) err = btintel_enter_mfg(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = btintel_set_diag(hdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = btintel_exit_mfg(hdev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EXPORT_SYMBOL_GPL(btintel_set_diag_mfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void btintel_hw_error(struct hci_dev *hdev, u8 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 type = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bt_dev_err(hdev, "Hardware error 0x%2.2x", code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bt_dev_err(hdev, "Reset after hardware error failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bt_dev_err(hdev, "Retrieving Intel exception info failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (skb->len != 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bt_dev_err(hdev, "Exception info size mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bt_dev_err(hdev, "Exception info %s", (char *)(skb->data + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EXPORT_SYMBOL_GPL(btintel_hw_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const char *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (ver->fw_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) variant = "Bootloader";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 0x23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) variant = "Firmware";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bt_dev_info(hdev, "%s revision %u.%u build %u week %u %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ver->fw_build_num, ver->fw_build_ww,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 2000 + ver->fw_build_yy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL_GPL(btintel_version_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) while (plen > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cmd_param[0] = fragment_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) memcpy(cmd_param + 1, param, fragment_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cmd_param, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (IS_ERR(skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) plen -= fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) param += fragment_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) EXPORT_SYMBOL_GPL(btintel_secure_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const u8 *fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) err = request_firmware_direct(&fw, ddc_name, &hdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ddc_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) fw_ptr = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* DDC file contains one or more DDC structure which has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) while (fw->size > fw_ptr - fw->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 cmd_plen = fw_ptr[0] + sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) fw_ptr += cmd_plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bt_dev_info(hdev, "Applying Intel DDC parameters completed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EXPORT_SYMBOL_GPL(btintel_load_ddc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int btintel_set_event_mask(struct hci_dev *hdev, bool debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mask[1] |= 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bt_dev_err(hdev, "Setting Intel event mask failed (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) EXPORT_SYMBOL_GPL(btintel_set_event_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int err, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) err = btintel_enter_mfg(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = btintel_set_event_mask(hdev, debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = btintel_exit_mfg(hdev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bt_dev_err(hdev, "Reading Intel version information failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (skb->len != sizeof(*ver)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bt_dev_err(hdev, "Intel version event size mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) memcpy(ver, skb->data, sizeof(*ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EXPORT_SYMBOL_GPL(btintel_read_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void btintel_version_info_tlv(struct hci_dev *hdev, struct intel_version_tlv *version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const char *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) switch (version->img_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) variant = "Bootloader";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bt_dev_info(hdev, "Device revision is %u", version->dev_rev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bt_dev_info(hdev, "Secure boot is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) version->secure_boot ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bt_dev_info(hdev, "OTP lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) version->otp_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bt_dev_info(hdev, "API lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) version->api_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bt_dev_info(hdev, "Debug lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) version->debug_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bt_dev_info(hdev, "Minimum firmware build %u week %u %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) version->min_fw_build_nn, version->min_fw_build_cw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 2000 + version->min_fw_build_yy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) variant = "Firmware";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bt_dev_err(hdev, "Unsupported image type(%02x)", version->img_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bt_dev_info(hdev, "%s timestamp %u.%u buildtype %u build %u", variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 2000 + (version->timestamp >> 8), version->timestamp & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) version->build_type, version->build_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) EXPORT_SYMBOL_GPL(btintel_version_info_tlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int btintel_read_version_tlv(struct hci_dev *hdev, struct intel_version_tlv *version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const u8 param[1] = { 0xFF };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) skb = __hci_cmd_sync(hdev, 0xfc05, 1, param, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bt_dev_err(hdev, "Reading Intel version information failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (skb->data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bt_dev_err(hdev, "Intel Read Version command failed (%02x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) skb->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Consume Command Complete Status field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) skb_pull(skb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Event parameters contatin multiple TLVs. Read each of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * and only keep the required data. Also, it use existing legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * version field like hw_platform, hw_variant, and fw_variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * to keep the existing setup flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) while (skb->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct intel_tlv *tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tlv = (struct intel_tlv *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) switch (tlv->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case INTEL_TLV_CNVI_TOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) version->cnvi_top = get_unaligned_le32(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case INTEL_TLV_CNVR_TOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) version->cnvr_top = get_unaligned_le32(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case INTEL_TLV_CNVI_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) version->cnvi_bt = get_unaligned_le32(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case INTEL_TLV_CNVR_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) version->cnvr_bt = get_unaligned_le32(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case INTEL_TLV_DEV_REV_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) version->dev_rev_id = get_unaligned_le16(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case INTEL_TLV_IMAGE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) version->img_type = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case INTEL_TLV_TIME_STAMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) version->timestamp = get_unaligned_le16(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case INTEL_TLV_BUILD_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) version->build_type = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case INTEL_TLV_BUILD_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) version->build_num = get_unaligned_le32(tlv->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case INTEL_TLV_SECURE_BOOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) version->secure_boot = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case INTEL_TLV_OTP_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) version->otp_lock = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case INTEL_TLV_API_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) version->api_lock = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case INTEL_TLV_DEBUG_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) version->debug_lock = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case INTEL_TLV_MIN_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) version->min_fw_build_nn = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) version->min_fw_build_cw = tlv->val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) version->min_fw_build_yy = tlv->val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case INTEL_TLV_LIMITED_CCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) version->limited_cce = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case INTEL_TLV_SBE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) version->sbe_type = tlv->val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case INTEL_TLV_OTP_BDADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memcpy(&version->otp_bd_addr, tlv->val, tlv->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Ignore rest of information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* consume the current tlv and move to next*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) skb_pull(skb, tlv->len + sizeof(*tlv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) EXPORT_SYMBOL_GPL(btintel_read_version_tlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* ------- REGMAP IBT SUPPORT ------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define IBT_REG_MODE_8BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define IBT_REG_MODE_16BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define IBT_REG_MODE_32BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct regmap_ibt_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __u16 op_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __u16 op_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct ibt_cp_reg_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct ibt_rp_reg_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int regmap_ibt_read(void *context, const void *addr, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct regmap_ibt_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ibt_cp_reg_access cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ibt_rp_reg_access *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (reg_size != sizeof(__le32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) switch (val_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cp.mode = IBT_REG_MODE_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cp.mode = IBT_REG_MODE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cp.mode = IBT_REG_MODE_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* regmap provides a little-endian formatted addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cp.addr = *(__le32 *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cp.len = val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) le32_to_cpu(cp.addr), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (skb->len != sizeof(*rp) + val_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) le32_to_cpu(cp.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rp = (struct ibt_rp_reg_access *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (rp->addr != cp.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) le32_to_cpu(rp->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) memcpy(val, rp->data, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int regmap_ibt_gather_write(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) const void *addr, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) const void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct regmap_ibt_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct ibt_cp_reg_access *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int plen = sizeof(*cp) + val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (reg_size != sizeof(__le32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) switch (val_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mode = IBT_REG_MODE_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mode = IBT_REG_MODE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mode = IBT_REG_MODE_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cp = kmalloc(plen, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!cp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* regmap provides a little-endian formatted addr/value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cp->addr = *(__le32 *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cp->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cp->len = val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) memcpy(&cp->data, val, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) le32_to_cpu(cp->addr), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) kfree(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int regmap_ibt_write(void *context, const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* data contains register+value, since we only support 32bit addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * minimum data size is 4 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (WARN_ONCE(count < 4, "Invalid register access"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void regmap_ibt_free_context(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) kfree(context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct regmap_bus regmap_ibt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .read = regmap_ibt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .write = regmap_ibt_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .gather_write = regmap_ibt_gather_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .free_context = regmap_ibt_free_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Config is the same for all register regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct regmap_config regmap_ibt_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .name = "btintel_regmap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u16 opcode_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct regmap_ibt_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) opcode_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ctx->op_read = opcode_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ctx->op_write = opcode_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ctx->hdev = hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return regmap_init(&hdev->dev, ®map_ibt, ctx, ®map_ibt_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) EXPORT_SYMBOL_GPL(btintel_regmap_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct intel_reset params = { 0x00, 0x01, 0x00, 0x01, 0x00000000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) params.boot_param = cpu_to_le32(boot_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), ¶ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) bt_dev_err(hdev, "Failed to send Intel Reset command");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) EXPORT_SYMBOL_GPL(btintel_send_intel_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int btintel_read_boot_params(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct intel_boot_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (skb->len != sizeof(*params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bt_dev_err(hdev, "Intel boot parameters size mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) memcpy(params, skb->data, sizeof(*params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (params->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bt_dev_err(hdev, "Intel boot parameters command failed (%02x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) params->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -bt_to_errno(params->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bt_dev_info(hdev, "Device revision is %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) le16_to_cpu(params->dev_revid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bt_dev_info(hdev, "Secure boot is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) params->secure_boot ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bt_dev_info(hdev, "OTP lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) params->otp_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) bt_dev_info(hdev, "API lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) params->api_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bt_dev_info(hdev, "Debug lock is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) params->debug_lock ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) bt_dev_info(hdev, "Minimum firmware build %u week %u %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) params->min_fw_build_nn, params->min_fw_build_cw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 2000 + params->min_fw_build_yy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) EXPORT_SYMBOL_GPL(btintel_read_boot_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int btintel_sfi_rsa_header_secure_send(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Start the firmware download transaction with the Init fragment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * represented by the 128 bytes of CSS header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) err = btintel_secure_send(hdev, 0x00, 128, fw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) bt_dev_err(hdev, "Failed to send firmware header (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Send the 256 bytes of public key information from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * as the PKey fragment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) err = btintel_secure_send(hdev, 0x03, 256, fw->data + 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Send the 256 bytes of signature information from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * as the Sign fragment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) err = btintel_secure_send(hdev, 0x02, 256, fw->data + 388);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) bt_dev_err(hdev, "Failed to send firmware signature (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int btintel_sfi_ecdsa_header_secure_send(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Start the firmware download transaction with the Init fragment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * represented by the 128 bytes of CSS header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err = btintel_secure_send(hdev, 0x00, 128, fw->data + 644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) bt_dev_err(hdev, "Failed to send firmware header (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Send the 96 bytes of public key information from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * as the PKey fragment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) err = btintel_secure_send(hdev, 0x03, 96, fw->data + 644 + 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Send the 96 bytes of signature information from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * as the Sign fragment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) err = btintel_secure_send(hdev, 0x02, 96, fw->data + 644 + 224);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) bt_dev_err(hdev, "Failed to send firmware signature (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int btintel_download_firmware_payload(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) const struct firmware *fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 *boot_param, size_t offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const u8 *fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 frag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) fw_ptr = fw->data + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) frag_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) while (fw_ptr - fw->data < fw->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct hci_command_hdr *cmd = (void *)(fw_ptr + frag_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Each SKU has a different reset parameter to use in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * HCI_Intel_Reset command and it is embedded in the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * data. So, instead of using static value per SKU, check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * the firmware data and save it for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (le16_to_cpu(cmd->opcode) == 0xfc0e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* The boot parameter is the first 32-bit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * and rest of 3 octets are reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) *boot_param = get_unaligned_le32(fw_ptr + sizeof(*cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) bt_dev_dbg(hdev, "boot_param=0x%x", *boot_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) frag_len += sizeof(*cmd) + cmd->plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* The parameter length of the secure send command requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * a 4 byte alignment. It happens so that the firmware file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * contains proper Intel_NOP commands to align the fragments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Send set of commands with 4 byte alignment from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * firmware data buffer as a single Data fragement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!(frag_len % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) err = btintel_secure_send(hdev, 0x01, frag_len, fw_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) bt_dev_err(hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "Failed to send firmware data (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) fw_ptr += frag_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) frag_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int btintel_download_firmware(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) const struct firmware *fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 *boot_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) err = btintel_sfi_rsa_header_secure_send(hdev, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return btintel_download_firmware_payload(hdev, fw, boot_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) RSA_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) EXPORT_SYMBOL_GPL(btintel_download_firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int btintel_download_firmware_newgen(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) const struct firmware *fw, u32 *boot_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u8 hw_variant, u8 sbe_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u32 css_header_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* iBT hardware variants 0x0b, 0x0c, 0x11, 0x12, 0x13, 0x14 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * only RSA secure boot engine. Hence, the corresponding sfi file will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * have RSA header of 644 bytes followed by Command Buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * iBT hardware variants 0x17, 0x18 onwards support both RSA and ECDSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * secure boot engine. As a result, the corresponding sfi file will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * have RSA header of 644, ECDSA header of 320 bytes followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * Command Buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * CSS Header byte positions 0x08 to 0x0B represent the CSS Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * version: RSA(0x00010000) , ECDSA (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) css_header_ver = get_unaligned_le32(fw->data + CSS_HEADER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (css_header_ver != 0x00010000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) bt_dev_err(hdev, "Invalid CSS Header version");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (hw_variant <= 0x14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (sbe_type != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) bt_dev_err(hdev, "Invalid SBE type for hardware variant (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hw_variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) err = btintel_sfi_rsa_header_secure_send(hdev, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) err = btintel_download_firmware_payload(hdev, fw, boot_param, RSA_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else if (hw_variant >= 0x17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Check if CSS header for ECDSA follows the RSA header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (fw->data[ECDSA_OFFSET] != 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Check if the CSS Header version is ECDSA(0x00020000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) css_header_ver = get_unaligned_le32(fw->data + ECDSA_OFFSET + CSS_HEADER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (css_header_ver != 0x00020000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) bt_dev_err(hdev, "Invalid CSS Header version");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (sbe_type == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) err = btintel_sfi_rsa_header_secure_send(hdev, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) err = btintel_download_firmware_payload(hdev, fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) boot_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RSA_HEADER_LEN + ECDSA_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else if (sbe_type == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = btintel_sfi_ecdsa_header_secure_send(hdev, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) err = btintel_download_firmware_payload(hdev, fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) boot_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RSA_HEADER_LEN + ECDSA_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) EXPORT_SYMBOL_GPL(btintel_download_firmware_newgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) void btintel_reset_to_bootloader(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct intel_reset params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Send Intel Reset command. This will result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * re-enumeration of BT controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Intel Reset parameter description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * reset_type : 0x00 (Soft reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * 0x01 (Hard reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * patch_enable : 0x00 (Do not enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * 0x01 (Enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * ddc_reload : 0x00 (Do not reload),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * 0x01 (Reload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * boot_option: 0x00 (Current image),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * 0x01 (Specified boot address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * boot_param: Boot address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) params.reset_type = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) params.patch_enable = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) params.ddc_reload = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) params.boot_option = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) params.boot_param = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ¶ms, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bt_dev_err(hdev, "FW download error recovery failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) bt_dev_info(hdev, "Intel reset sent to retry FW download");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Current Intel BT controllers(ThP/JfP) hold the USB reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * lines for 2ms when it receives Intel Reset in bootloader mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * Whereas, the upcoming Intel BT controllers will hold USB reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * for 150ms. To keep the delay generic, 150ms is chosen here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) EXPORT_SYMBOL_GPL(btintel_reset_to_bootloader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int btintel_read_debug_features(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct intel_debug_features *features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 page_no = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Intel controller supports two pages, each page is of 128-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * feature bit mask. And each bit defines specific feature support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) skb = __hci_cmd_sync(hdev, 0xfca6, sizeof(page_no), &page_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) bt_dev_err(hdev, "Reading supported features failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (skb->len != (sizeof(features->page1) + 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bt_dev_err(hdev, "Supported features event size mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) memcpy(features->page1, skb->data + 3, sizeof(features->page1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Read the supported features page2 if required in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) EXPORT_SYMBOL_GPL(btintel_read_debug_features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int btintel_set_debug_features(struct hci_dev *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const struct intel_debug_features *features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 mask[11] = { 0x0a, 0x92, 0x02, 0x07, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) 0x00, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!(features->page1[0] & 0x3f)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) bt_dev_info(hdev, "Telemetry exception format not supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) skb = __hci_cmd_sync(hdev, 0xfc8b, 11, mask, HCI_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (IS_ERR(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bt_dev_err(hdev, "Setting Intel telemetry ddc write event mask failed (%ld)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PTR_ERR(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return PTR_ERR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) EXPORT_SYMBOL_GPL(btintel_set_debug_features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MODULE_VERSION(VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MODULE_FIRMWARE("intel/ibt-11-5.sfi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) MODULE_FIRMWARE("intel/ibt-11-5.ddc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) MODULE_FIRMWARE("intel/ibt-12-16.sfi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) MODULE_FIRMWARE("intel/ibt-12-16.ddc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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