^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bluetooth driver for the Anycom BlueCard (LSE039/LSE041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001-2002 Marcel Holtmann <marcel@holtmann.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Software distributed under the License is distributed on an "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * implied. See the License for the specific language governing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * rights and limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <pcmcia/ciscode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <pcmcia/cisreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <net/bluetooth/bluetooth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <net/bluetooth/hci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* ======================== Module parameters ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_DESCRIPTION("Bluetooth driver for the Anycom BlueCard (LSE039/LSE041)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* ======================== Local structures ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct bluecard_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pcmcia_device *p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spinlock_t lock; /* For serializing operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct timer_list timer; /* For LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sk_buff_head txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long rx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long rx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sk_buff *rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned char ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long hw_state; /* Status of the hardware and LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int bluecard_config(struct pcmcia_device *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void bluecard_release(struct pcmcia_device *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void bluecard_detach(struct pcmcia_device *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Default baud rate: 57600, 115200, 230400 or 460800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEFAULT_BAUD_RATE 230400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Hardware states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CARD_READY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CARD_ACTIVITY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CARD_HAS_PCCARD_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CARD_HAS_POWER_LED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CARD_HAS_ACTIVITY_LED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Transmit states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XMIT_SENDING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XMIT_WAKEUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XMIT_BUFFER_NUMBER 5 /* unset = buffer one, set = buffer two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XMIT_BUF_ONE_READY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XMIT_BUF_TWO_READY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XMIT_SENDING_READY 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Receiver states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RECV_WAIT_PACKET_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RECV_WAIT_EVENT_HEADER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RECV_WAIT_ACL_HEADER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RECV_WAIT_SCO_HEADER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RECV_WAIT_DATA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Special packet types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PKT_BAUD_RATE_57600 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PKT_BAUD_RATE_115200 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PKT_BAUD_RATE_230400 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PKT_BAUD_RATE_460800 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* These are the register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define REG_COMMAND 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define REG_INTERRUPT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REG_CONTROL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define REG_RX_CONTROL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_CARD_RESET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_LED_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* REG_COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_COMMAND_TX_BUF_ONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define REG_COMMAND_TX_BUF_TWO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define REG_COMMAND_RX_BUF_ONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REG_COMMAND_RX_BUF_TWO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REG_COMMAND_RX_WIN_ONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_COMMAND_RX_WIN_TWO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* REG_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define REG_CONTROL_BAUD_RATE_57600 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_CONTROL_BAUD_RATE_115200 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_CONTROL_BAUD_RATE_230400 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REG_CONTROL_BAUD_RATE_460800 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REG_CONTROL_RTS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_CONTROL_BT_ON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REG_CONTROL_BT_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define REG_CONTROL_BT_RES_PU 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REG_CONTROL_INTERRUPT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define REG_CONTROL_CARD_RESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* REG_RX_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RTS_LEVEL_SHIFT_BITS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* ======================== LED handling routines ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void bluecard_activity_led_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct bluecard_info *info = from_timer(info, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (test_bit(CARD_ACTIVITY, &(info->hw_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* leave LED in inactive state for HZ/10 for blink effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clear_bit(CARD_ACTIVITY, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mod_timer(&(info->timer), jiffies + HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Disable activity LED, enable power LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) outb(0x08 | 0x20, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void bluecard_enable_activity_led(struct bluecard_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* don't disturb running blink timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (timer_pending(&(info->timer)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) set_bit(CARD_ACTIVITY, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (test_bit(CARD_HAS_ACTIVITY_LED, &(info->hw_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Enable activity LED, keep power LED enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) outb(0x18 | 0x60, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Disable power LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) outb(0x00, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Stop the LED after HZ/10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mod_timer(&(info->timer), jiffies + HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* ======================== Interrupt handling ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int bluecard_write(unsigned int iobase, unsigned int offset, __u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i, actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) actual = (len > 15) ? 15 : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb_p(actual, iobase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; i < actual; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) outb_p(buf[i], iobase + offset + i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void bluecard_write_wakeup(struct bluecard_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BT_ERR("Unknown device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!test_bit(XMIT_SENDING_READY, &(info->tx_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (test_and_set_bit(XMIT_SENDING, &(info->tx_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) set_bit(XMIT_WAKEUP, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long ready_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) register struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clear_bit(XMIT_WAKEUP, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!pcmcia_dev_present(info->p_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (test_bit(XMIT_BUFFER_NUMBER, &(info->tx_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!test_bit(XMIT_BUF_TWO_READY, &(info->tx_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) offset = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) command = REG_COMMAND_TX_BUF_TWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ready_bit = XMIT_BUF_TWO_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!test_bit(XMIT_BUF_ONE_READY, &(info->tx_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) offset = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) command = REG_COMMAND_TX_BUF_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ready_bit = XMIT_BUF_ONE_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) skb = skb_dequeue(&(info->txq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (hci_skb_pkt_type(skb) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Disable RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) info->ctrl_reg |= REG_CONTROL_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Activate LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bluecard_enable_activity_led(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Send frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) len = bluecard_write(iobase, offset, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Tell the FPGA to send the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) outb_p(command, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Mark the buffer as dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clear_bit(ready_bit, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (hci_skb_pkt_type(skb) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DEFINE_WAIT(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned char baud_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (hci_skb_pkt_type(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case PKT_BAUD_RATE_460800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) baud_reg = REG_CONTROL_BAUD_RATE_460800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case PKT_BAUD_RATE_230400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) baud_reg = REG_CONTROL_BAUD_RATE_230400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case PKT_BAUD_RATE_115200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) baud_reg = REG_CONTROL_BAUD_RATE_115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case PKT_BAUD_RATE_57600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) baud_reg = REG_CONTROL_BAUD_RATE_57600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Wait until the command reaches the baseband */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Set baud on baseband */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) info->ctrl_reg &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) info->ctrl_reg |= baud_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Enable RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) info->ctrl_reg &= ~REG_CONTROL_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Wait before the next HCI packet can be send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (len == skb->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) skb_pull(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) skb_queue_head(&(info->txq), skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) info->hdev->stat.byte_tx += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Change buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) change_bit(XMIT_BUFFER_NUMBER, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } while (test_bit(XMIT_WAKEUP, &(info->tx_state)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clear_bit(XMIT_SENDING, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int bluecard_read(unsigned int iobase, unsigned int offset, __u8 *buf, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i, n, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) outb(REG_COMMAND_RX_WIN_ONE, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) len = inb(iobase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) while (n < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (i == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) outb(REG_COMMAND_RX_WIN_TWO, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) buf[n] = inb(iobase + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void bluecard_receive(struct bluecard_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned char buf[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BT_ERR("Unknown device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (test_bit(XMIT_SENDING_READY, &(info->tx_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bluecard_enable_activity_led(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) len = bluecard_read(iobase, offset, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Allocate packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!info->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) info->rx_state = RECV_WAIT_PACKET_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) info->rx_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) info->rx_skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!info->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) BT_ERR("Can't allocate mem for new packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (info->rx_state == RECV_WAIT_PACKET_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hci_skb_pkt_type(info->rx_skb) = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) switch (hci_skb_pkt_type(info->rx_skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* init packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (offset != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) set_bit(XMIT_BUF_ONE_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) set_bit(XMIT_BUF_TWO_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) set_bit(XMIT_SENDING_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bluecard_write_wakeup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) kfree_skb(info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) info->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case HCI_EVENT_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) info->rx_state = RECV_WAIT_EVENT_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) info->rx_count = HCI_EVENT_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case HCI_ACLDATA_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) info->rx_state = RECV_WAIT_ACL_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) info->rx_count = HCI_ACL_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case HCI_SCODATA_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) info->rx_state = RECV_WAIT_SCO_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) info->rx_count = HCI_SCO_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* unknown packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BT_ERR("Unknown HCI packet with type 0x%02x received",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) hci_skb_pkt_type(info->rx_skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) info->hdev->stat.err_rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) kfree_skb(info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) info->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) skb_put_u8(info->rx_skb, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) info->rx_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (info->rx_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int dlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct hci_event_hdr *eh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct hci_acl_hdr *ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct hci_sco_hdr *sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) switch (info->rx_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case RECV_WAIT_EVENT_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) eh = hci_event_hdr(info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) info->rx_state = RECV_WAIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) info->rx_count = eh->plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case RECV_WAIT_ACL_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ah = hci_acl_hdr(info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dlen = __le16_to_cpu(ah->dlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) info->rx_state = RECV_WAIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) info->rx_count = dlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case RECV_WAIT_SCO_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sh = hci_sco_hdr(info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) info->rx_state = RECV_WAIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) info->rx_count = sh->dlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case RECV_WAIT_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hci_recv_frame(info->hdev, info->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) info->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) info->hdev->stat.byte_rx += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static irqreturn_t bluecard_interrupt(int irq, void *dev_inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct bluecard_info *info = dev_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!info || !info->hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* our irq handler is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!test_bit(CARD_READY, &(info->hw_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spin_lock(&(info->lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) info->ctrl_reg &= ~REG_CONTROL_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg = inb(iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if ((reg != 0x00) && (reg != 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (reg & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bluecard_receive(info, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) outb(0x04, iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) outb(REG_COMMAND_RX_BUF_ONE, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (reg & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bluecard_receive(info, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) outb(0x08, iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) outb(REG_COMMAND_RX_BUF_TWO, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (reg & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) set_bit(XMIT_BUF_ONE_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) outb(0x01, iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) bluecard_write_wakeup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (reg & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) set_bit(XMIT_BUF_TWO_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) outb(0x02, iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) bluecard_write_wakeup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) info->ctrl_reg |= REG_CONTROL_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spin_unlock(&(info->lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* ======================== Device specific HCI commands ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int bluecard_hci_set_baud_rate(struct hci_dev *hdev, int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct bluecard_info *info = hci_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Ericsson baud rate command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned char cmd[] = { HCI_COMMAND_PKT, 0x09, 0xfc, 0x01, 0x03 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) BT_ERR("Can't allocate mem for new packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) switch (baud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 460800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cmd[4] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hci_skb_pkt_type(skb) = PKT_BAUD_RATE_460800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case 230400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cmd[4] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) hci_skb_pkt_type(skb) = PKT_BAUD_RATE_230400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case 115200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) cmd[4] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hci_skb_pkt_type(skb) = PKT_BAUD_RATE_115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 57600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cmd[4] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hci_skb_pkt_type(skb) = PKT_BAUD_RATE_57600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) skb_put_data(skb, cmd, sizeof(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) skb_queue_tail(&(info->txq), skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) bluecard_write_wakeup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* ======================== HCI interface ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int bluecard_hci_flush(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct bluecard_info *info = hci_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Drop TX queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) skb_queue_purge(&(info->txq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int bluecard_hci_open(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct bluecard_info *info = hci_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (test_bit(CARD_HAS_PCCARD_ID, &(info->hw_state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bluecard_hci_set_baud_rate(hdev, DEFAULT_BAUD_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Enable power LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) outb(0x08 | 0x20, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int bluecard_hci_close(struct hci_dev *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct bluecard_info *info = hci_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) bluecard_hci_flush(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Stop LED timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) del_timer_sync(&(info->timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Disable power LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) outb(0x00, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int bluecard_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct bluecard_info *info = hci_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) switch (hci_skb_pkt_type(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case HCI_COMMAND_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hdev->stat.cmd_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case HCI_ACLDATA_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hdev->stat.acl_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case HCI_SCODATA_PKT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) hdev->stat.sco_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Prepend skb with frame type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) skb_queue_tail(&(info->txq), skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) bluecard_write_wakeup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* ======================== Card services HCI interaction ======================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int bluecard_open(struct bluecard_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned char id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) spin_lock_init(&(info->lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) timer_setup(&info->timer, bluecard_activity_led_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) skb_queue_head_init(&(info->txq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) info->rx_state = RECV_WAIT_PACKET_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) info->rx_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) info->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Initialize HCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) hdev = hci_alloc_dev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!hdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) BT_ERR("Can't allocate HCI device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) info->hdev = hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) hdev->bus = HCI_PCCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hci_set_drvdata(hdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SET_HCIDEV_DEV(hdev, &info->p_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hdev->open = bluecard_hci_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hdev->close = bluecard_hci_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hdev->flush = bluecard_hci_flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hdev->send = bluecard_hci_send_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) id = inb(iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if ((id & 0x0f) == 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) set_bit(CARD_HAS_PCCARD_ID, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (id & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) set_bit(CARD_HAS_POWER_LED, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (id & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) set_bit(CARD_HAS_ACTIVITY_LED, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Reset card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Turn FPGA off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) outb(0x80, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Wait some time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Turn FPGA on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) outb(0x00, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Activate card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) info->ctrl_reg = REG_CONTROL_BT_ON | REG_CONTROL_BT_RES_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) outb(0xff, iobase + REG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) info->ctrl_reg |= REG_CONTROL_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if ((id & 0x0f) == 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Disable RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) info->ctrl_reg |= REG_CONTROL_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Set baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) info->ctrl_reg |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Enable RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) info->ctrl_reg &= ~REG_CONTROL_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) set_bit(XMIT_BUF_ONE_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) set_bit(XMIT_BUF_TWO_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) set_bit(XMIT_SENDING_READY, &(info->tx_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Start the RX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) outb(REG_COMMAND_RX_BUF_ONE, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) outb(REG_COMMAND_RX_BUF_TWO, iobase + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Signal that the hardware is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) set_bit(CARD_READY, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Drop TX queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) skb_queue_purge(&(info->txq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Control the point at which RTS is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) outb((0x0f << RTS_LEVEL_SHIFT_BITS) | 1, iobase + REG_RX_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Timeout before it is safe to send the first HCI packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) msleep(1250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Register HCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (hci_register_dev(hdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) BT_ERR("Can't register HCI device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) info->hdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) hci_free_dev(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int bluecard_close(struct bluecard_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int iobase = info->p_dev->resource[0]->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct hci_dev *hdev = info->hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bluecard_hci_close(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) clear_bit(CARD_READY, &(info->hw_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Reset card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) outb(info->ctrl_reg, iobase + REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Turn FPGA off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) outb(0x80, iobase + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hci_unregister_dev(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) hci_free_dev(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int bluecard_probe(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct bluecard_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Create new info device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) info = devm_kzalloc(&link->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) info->p_dev = link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) link->priv = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) link->config_flags |= CONF_ENABLE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return bluecard_config(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void bluecard_detach(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) bluecard_release(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int bluecard_config(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct bluecard_info *info = link->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) link->config_index = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) link->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) link->resource[0]->end = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) link->io_lines = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) for (n = 0; n < 0x400; n += 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) link->resource[0]->start = n ^ 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) i = pcmcia_request_io(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) i = pcmcia_request_irq(link, bluecard_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) i = pcmcia_enable_device(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (bluecard_open(info) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) bluecard_release(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static void bluecard_release(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct bluecard_info *info = link->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) bluecard_close(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) del_timer_sync(&(info->timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pcmcia_disable_device(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const struct pcmcia_device_id bluecard_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PCMCIA_DEVICE_PROD_ID12("BlueCard", "LSE041", 0xbaf16fbf, 0x657cc15e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PCMCIA_DEVICE_PROD_ID12("BTCFCARD", "LSE139", 0xe3987764, 0x2524b59c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PCMCIA_DEVICE_PROD_ID12("WSS", "LSE039", 0x0a0736ec, 0x24e6dfab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PCMCIA_DEVICE_NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MODULE_DEVICE_TABLE(pcmcia, bluecard_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static struct pcmcia_driver bluecard_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .name = "bluecard_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .probe = bluecard_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .remove = bluecard_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .id_table = bluecard_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) module_pcmcia_driver(bluecard_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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