^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file contains defines for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Micro Memory MM5415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * family PCI Memory Module with Battery Backup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright Micro Memory INC 2001. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _DRIVERS_BLOCK_MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _DRIVERS_BLOCK_MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IRQ_TIMEOUT (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* CSR register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MEMCTRLSTATUS_MAGIC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MM_MAGIC_VALUE (unsigned char)0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MEMCTRLSTATUS_BATTERY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BATTERY_1_DISABLED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BATTERY_1_FAILURE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BATTERY_2_DISABLED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BATTERY_2_FAILURE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MEMCTRLSTATUS_MEMORY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MEM_128_MB 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MEM_256_MB 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MEM_512_MB 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MEM_1_GB 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MEM_2_GB 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MEMCTRLCMD_LEDCTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LED_REMOVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LED_FAULT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LED_POWER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LED_FLIP 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LED_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LED_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LED_FLASH_3_5 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LED_FLASH_7_0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LED_POWER_ON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LED_POWER_OFF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USER_BIT1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USER_BIT2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MEMORY_INITIALIZED USER_BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MEMCTRLCMD_ERRCTRL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EDC_NONE_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EDC_NONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EDC_STORE_READ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EDC_STORE_CORRECT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MEMCTRLCMD_ERRCNT 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MEMCTRLCMD_ERRSTATUS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ERROR_DATA_LOG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ERROR_ADDR_LOG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ERROR_COUNT 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ERROR_SYNDROME 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ERROR_CHECK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMA_PCI_ADDR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMA_LOCAL_ADDR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_TRANSFER_SIZE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA_DESCRIPTOR_ADDR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA_SEMAPHORE_ADDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DMA_STATUS_CTRL 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMASCR_GO 0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMASCR_TRANSFER_READ 0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMASCR_CHAIN_EN 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DMASCR_SEM_EN 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMASCR_DMA_COMP_EN 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DMASCR_CHAIN_COMP_EN 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DMASCR_ERR_INT_EN 0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DMASCR_PARITY_INT_EN 0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DMASCR_ANY_ERR 0x00800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DMASCR_MBE_ERR 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMASCR_PARITY_ERR_REP 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMASCR_PARITY_ERR_DET 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMASCR_SYSTEM_ERR_SIG 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DMASCR_TARGET_ABT 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMASCR_MASTER_ABT 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DMASCR_DMA_COMPLETE 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DMASCR_CHAIN_COMPLETE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DMA READ OPERATIONS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DMASCR_READ 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DMASCR_READLINE 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DMASCR_READMULTI 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WINDOWMAP_WINNUM 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMA_READ_FROM_HOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DMA_WRITE_TO_HOST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mm_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __le64 pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __le64 local_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le32 transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 zero1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le64 next_desc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __le64 sem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __le32 control_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 zero2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dma_addr_t data_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Copy of the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __le64 sem_control_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } __attribute__((aligned(8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* bits for card->flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UM_FLAG_DMA_IN_REGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UM_FLAG_NO_BYTE_STATUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UM_FLAG_NO_BATTREG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define UM_FLAG_NO_BATT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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