Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2012 STEC, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2017 Western Digital Corporation or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef SKD_S1120_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define SKD_S1120_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Q-channel, 64-bit r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define FIT_Q_COMMAND			0x400u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define FIT_QCMD_QID_MASK		(0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define  FIT_QCMD_QID0			(0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define  FIT_QCMD_QID_NORMAL		FIT_QCMD_QID0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define  FIT_QCMD_QID1			(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define  FIT_QCMD_QID2			(0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define  FIT_QCMD_QID3			(0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define  FIT_QCMD_FLUSH_QUEUE		(0ull)	/* add QID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define  FIT_QCMD_MSGSIZE_MASK		(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define  FIT_QCMD_MSGSIZE_64		(0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define  FIT_QCMD_MSGSIZE_128		(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  FIT_QCMD_MSGSIZE_256		(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  FIT_QCMD_MSGSIZE_512		(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  FIT_QCMD_ALIGN			L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * Control, 32-bit r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define FIT_CONTROL			0x500u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define  FIT_CR_HARD_RESET		(1u << 0u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define  FIT_CR_SOFT_RESET		(1u << 1u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  FIT_CR_DIS_TIMESTAMPS		(1u << 6u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define  FIT_CR_ENABLE_INTERRUPTS	(1u << 7u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Status, 32-bit, r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define FIT_STATUS			0x510u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define FIT_SR_DRIVE_STATE_MASK		0x000000FFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	FIT_SR_SIGNATURE		(0xFF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	FIT_SR_PIO_DMA			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define FIT_SR_DRIVE_OFFLINE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define FIT_SR_DRIVE_INIT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* #define FIT_SR_DRIVE_READY		0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define FIT_SR_DRIVE_ONLINE		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define FIT_SR_DRIVE_BUSY		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define FIT_SR_DRIVE_FAULT		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define FIT_SR_DRIVE_DEGRADED		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define FIT_SR_PCIE_LINK_DOWN		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define FIT_SR_DRIVE_SOFT_RESET		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define FIT_SR_DRIVE_INIT_FAULT		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define FIT_SR_DRIVE_BUSY_SANITIZE	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define FIT_SR_DRIVE_BUSY_ERASE		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define FIT_SR_DRIVE_FW_BOOTING		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define FIT_SR_DRIVE_NEED_FW_DOWNLOAD	0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define FIT_SR_DEVICE_MISSING		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define FIT_SR__RESERVED		0xFFFFFF00u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * FIT_STATUS - Status register data definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define FIT_SR_STATE_MASK		(0xFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define FIT_SR_SIGNATURE		(0xFF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define FIT_SR_PIO_DMA			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define FIT_INT_STATUS_HOST		0x520u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  FIT_ISH_FW_STATE_CHANGE	(1u << 0u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define  FIT_ISH_COMPLETION_POSTED	(1u << 1u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define  FIT_ISH_MSG_FROM_DEV		(1u << 2u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define  FIT_ISH_UNDEFINED_3		(1u << 3u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define  FIT_ISH_UNDEFINED_4		(1u << 4u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define  FIT_ISH_Q0_FULL		(1u << 5u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define  FIT_ISH_Q1_FULL		(1u << 6u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define  FIT_ISH_Q2_FULL		(1u << 7u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  FIT_ISH_Q3_FULL		(1u << 8u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  FIT_ISH_QCMD_FIFO_OVERRUN	(1u << 9u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define  FIT_ISH_BAD_EXP_ROM_READ	(1u << 10u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define FIT_INT_DEF_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	(FIT_ISH_FW_STATE_CHANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 FIT_ISH_COMPLETION_POSTED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 FIT_ISH_MSG_FROM_DEV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 FIT_ISH_Q0_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 FIT_ISH_Q1_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 FIT_ISH_Q2_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 FIT_ISH_Q3_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 FIT_ISH_QCMD_FIFO_OVERRUN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 FIT_ISH_BAD_EXP_ROM_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define FIT_INT_QUEUE_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	(FIT_ISH_Q0_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 FIT_ISH_Q1_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 FIT_ISH_Q2_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 FIT_ISH_Q3_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSI_MSG_NWL_ERROR_0		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSI_MSG_NWL_ERROR_1		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSI_MSG_NWL_ERROR_2		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSI_MSG_NWL_ERROR_3		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSI_MSG_STATE_CHANGE		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSI_MSG_COMPLETION_POSTED	0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSI_MSG_MSG_FROM_DEV		0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSI_MSG_RESERVED_0		0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSI_MSG_RESERVED_1		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSI_MSG_QUEUE_0_FULL		0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSI_MSG_QUEUE_1_FULL		0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSI_MSG_QUEUE_2_FULL		0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSI_MSG_QUEUE_3_FULL		0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FIT_INT_RESERVED_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	(FIT_ISH_UNDEFINED_3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 FIT_ISH_UNDEFINED_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * Interrupt mask, 32-bit r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * Bit definitions are the same as FIT_INT_STATUS_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FIT_INT_MASK_HOST		0x528u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Message to device, 32-bit r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FIT_MSG_TO_DEVICE		0x540u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Message from device, 32-bit, r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FIT_MSG_FROM_DEVICE		0x548u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * 32-bit messages to/from device, composition/extraction macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FIT_MXD_CONS(TYPE, PARAM, DATA) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	((((TYPE)  & 0xFFu) << 24u) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	(((PARAM) & 0xFFu) << 16u) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	(((DATA)  & 0xFFFFu) << 0u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FIT_MXD_TYPE(MXD)		(((MXD) >> 24u) & 0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FIT_MXD_PARAM(MXD)		(((MXD) >> 16u) & 0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FIT_MXD_DATA(MXD)		(((MXD) >> 0u) & 0xFFFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * Types of messages to/from device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FIT_MTD_FITFW_INIT		0x01u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FIT_MTD_GET_CMDQ_DEPTH		0x02u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FIT_MTD_SET_COMPQ_DEPTH		0x03u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FIT_MTD_SET_COMPQ_ADDR		0x04u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FIT_MTD_ARM_QUEUE		0x05u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FIT_MTD_CMD_LOG_HOST_ID		0x07u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FIT_MTD_CMD_LOG_TIME_STAMP_LO	0x08u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FIT_MTD_CMD_LOG_TIME_STAMP_HI	0x09u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FIT_MFD_SMART_EXCEEDED		0x10u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FIT_MFD_POWER_DOWN		0x11u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FIT_MFD_OFFLINE			0x12u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FIT_MFD_ONLINE			0x13u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FIT_MFD_FW_RESTARTING		0x14u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FIT_MFD_PM_ACTIVE		0x15u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FIT_MFD_PM_STANDBY		0x16u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FIT_MFD_PM_SLEEP		0x17u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FIT_MFD_CMD_PROGRESS		0x18u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FIT_MTD_DEBUG			0xFEu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FIT_MFD_DEBUG			0xFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FIT_MFD_MASK			(0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FIT_MFD_DATA_MASK		(0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FIT_MFD_MSG(x)			(((x) >> 24) & FIT_MFD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FIT_MFD_DATA(x)			((x) & FIT_MFD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * (was Response buffer in docs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FIT_MSG_TO_DEVICE_ARG		0x580u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * Hardware (ASIC) version, 32-bit r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FIT_HW_VERSION			0x588u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * Scatter/gather list descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * 32-bytes and must be aligned on a 32-byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * All fields are in little endian order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct fit_sg_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	uint32_t control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	uint32_t byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	uint64_t host_side_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	uint64_t dev_side_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	uint64_t next_desc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FIT_SGD_CONTROL_NOT_LAST	0x000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FIT_SGD_CONTROL_LAST		0x40Eu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * Header at the beginning of a FIT message. The header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * is followed by SSDI requests each 64 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * A FIT message can be up to 512 bytes long and must start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * on a 64-byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct fit_msg_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	uint8_t protocol_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	uint8_t num_protocol_cmds_coalesced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	uint8_t _reserved[62];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define FIT_PROTOCOL_ID_FIT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FIT_PROTOCOL_ID_SSDI	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define FIT_PROTOCOL_ID_SOFIT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * Format of a completion entry. The completion queue is circular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * and must have at least as many entries as the maximum number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * of commands that may be issued to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * There are no head/tail pointers. The cycle value is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * infer the presence of new completion records.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * Initially the cycle in all entries is 0, the index is 0, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * the cycle value to expect is 1. When completions are added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * their cycle values are set to 1. When the index wraps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * cycle value to expect is incremented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * Command_context is opaque and taken verbatim from the SSDI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * All other fields are big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define FIT_PROTOCOL_VERSION_0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *  Protocol major version 1 completion entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  *  The major protocol version is found in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *  20-23 of the FIT_MTD_FITFW_INIT response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct fit_completion_entry_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	__be32		num_returned_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	uint16_t	tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	uint8_t		status;  /* SCSI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	uint8_t		cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FIT_PROTOCOL_VERSION_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define FIT_PROTOCOL_VERSION_CURRENT	FIT_PROTOCOL_VERSION_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct fit_comp_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	uint8_t		type:7; /* 00: Bits0-6 indicates the type of sense data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	uint8_t		valid:1; /* 00: Bit 7 := 1 ==> info field is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	uint8_t		reserved0; /* 01: Obsolete field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	uint8_t		key:4; /* 02: Bits0-3 indicate the sense key. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	uint8_t		reserved2:1; /* 02: Reserved bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	uint8_t		bad_length:1; /* 02: Incorrect Length Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	uint8_t		end_medium:1; /* 02: End of Medium */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	uint8_t		file_mark:1; /* 02: Filemark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	uint8_t		info[4]; /* 03: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	uint8_t		reserved1; /* 07: Additional Sense Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	uint8_t		cmd_spec[4]; /* 08: Command Specific Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	uint8_t		code; /* 0C: Additional Sense Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	uint8_t		qual; /* 0D: Additional Sense Code Qualifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	uint8_t		fruc; /* 0E: Field Replaceable Unit Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	uint8_t		sks_high:7; /* 0F: Sense Key Specific (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	uint8_t		sks_valid:1; /* 0F: Sense Key Specific Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	uint16_t	sks_low; /* 10: Sense Key Specific (LSW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	uint16_t	reserved3; /* 12: Part of additional sense bytes (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	uint16_t	uec; /* 14: Additional Sense Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	uint64_t	per __packed; /* 16: Additional Sense Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	uint8_t		reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Task management constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SOFT_TASK_SIMPLE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SOFT_TASK_HEAD_OF_QUEUE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SOFT_TASK_ORDERED		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Version zero has the last 32 bits reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * Version one has the last 32 bits sg_list_len_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct skd_command_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	__be64		sg_list_dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	uint16_t	tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	uint8_t		attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	uint8_t		add_cdb_len;     /* In 32 bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	__be32		sg_list_len_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct skd_scsi_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct		skd_command_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	unsigned char	cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*	unsigned char _reserved[16]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct driver_inquiry_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	uint8_t		peripheral_device_type:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	uint8_t		qualifier:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	uint8_t		page_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	__be16		page_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	__be16		pcie_bus_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	uint8_t		pcie_device_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	uint8_t		pcie_function_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	uint8_t		pcie_link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	uint8_t		pcie_link_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	__be16		pcie_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	__be16		pcie_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	__be16		pcie_subsystem_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	__be16		pcie_subsystem_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	uint8_t		reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	uint8_t		reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	uint8_t		driver_version_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	uint8_t		driver_version[0x14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif /* SKD_S1120_H */