^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Filename: rsxx_priv.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Philip Kelleher <pjk1939@linux.vnet.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2013 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __RSXX_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __RSXX_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "rsxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "rsxx_cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct proc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_DEVICE_ID_FS70_FLASH 0x04A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_FS80_FLASH 0x04AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RS70_PCI_REV_SUPPORTED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVER_NAME "rsxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION "4.0.3.2516"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Block size is 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RSXX_HW_BLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RSXX_HW_BLK_SIZE (1 << RSXX_HW_BLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RSXX_HW_BLK_MASK (RSXX_HW_BLK_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX_CREG_DATA8 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LOG_BUF_SIZE8 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RSXX_MAX_OUTSTANDING_CMDS 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RSXX_CS_IDX_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STATUS_BUFFER_SIZE8 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define COMMAND_BUFFER_SIZE8 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RSXX_MAX_TARGETS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dma_tracker_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* DMA Command/Status Buffer structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct rsxx_cs_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct rsxx_dma_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 crc_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 hard_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 soft_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 writes_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 writes_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reads_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 reads_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 reads_retried;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 discards_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 discards_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 done_rescheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 issue_rescheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 dma_sw_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 dma_hw_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 dma_cancelled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 sw_q_depth; /* Number of DMAs on the SW queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) atomic_t hw_q_depth; /* Number of DMAs queued to HW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct rsxx_dma_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct rsxx_cardinfo *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct rsxx_cs_buffer status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct rsxx_cs_buffer cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 e_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct workqueue_struct *issue_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct work_struct issue_dma_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct workqueue_struct *done_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct work_struct dma_done_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct timer_list activity_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dma_tracker_list *trackers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct rsxx_dma_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct mutex work_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rsxx_cardinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int eeh_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int isr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int ier_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rsxx_card_cfg config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int config_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Embedded CPU Communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct creg_cmd *active_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct workqueue_struct *creg_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct work_struct done_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int q_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Cache the creg status to prevent ioreads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 failed_cancel_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 creg_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } creg_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct timer_list cmd_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mutex reset_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } creg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) char tmp[MAX_CREG_DATA8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) char buf[LOG_BUF_SIZE8]; /* terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct workqueue_struct *event_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct work_struct event_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u64 size8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Lock the device attach/detach function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mutex dev_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Block Device Variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool bdev_attached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int disk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct request_queue *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct gendisk *gendisk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Used to convert a byte address to a device address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u64 lower_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u64 upper_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u64 upper_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u64 target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u64 target_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } _stripe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int dma_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int scrub_hard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int n_targets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct rsxx_dma_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum rsxx_pci_regmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) HWID = 0x00, /* Hardware Identification Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SCRATCH = 0x04, /* Scratch/Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RESET = 0x08, /* Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ISR = 0x10, /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IER = 0x14, /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IPR = 0x18, /* Interrupt Poll Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CB_ADD_LO = 0x20, /* Command Host Buffer Address [31:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CB_ADD_HI = 0x24, /* Command Host Buffer Address [63:32]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) HW_CMD_IDX = 0x28, /* Hardware Processed Command Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SW_CMD_IDX = 0x2C, /* Software Processed Command Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SB_ADD_LO = 0x30, /* Status Host Buffer Address [31:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SB_ADD_HI = 0x34, /* Status Host Buffer Address [63:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) HW_STATUS_CNT = 0x38, /* Hardware Status Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SW_STATUS_CNT = 0x3C, /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CREG_CMD = 0x40, /* CPU Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CREG_ADD = 0x44, /* CPU Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CREG_CNT = 0x48, /* CPU Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CREG_STAT = 0x4C, /* CPU Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CREG_DATA0 = 0x50, /* CPU Data Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CREG_DATA1 = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CREG_DATA2 = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CREG_DATA3 = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CREG_DATA4 = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CREG_DATA5 = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CREG_DATA6 = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CREG_DATA7 = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) INTR_COAL = 0x70, /* Interrupt Coalescing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) HW_ERROR = 0x74, /* Card Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PCI_DEBUG0 = 0x78, /* PCI Debug Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PCI_DEBUG1 = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PCI_DEBUG2 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PCI_DEBUG3 = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PCI_DEBUG4 = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PCI_DEBUG5 = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PCI_DEBUG6 = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PCI_DEBUG7 = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PCI_POWER_THROTTLE = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PERF_CTRL = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PERF_TIMER_LO = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PERF_TIMER_HI = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PERF_RD512_LO = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PERF_RD512_HI = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PERF_WR512_LO = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PERF_WR512_HI = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PCI_RECONFIG = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum rsxx_intr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CR_INTR_DMA0 = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CR_INTR_CREG = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CR_INTR_DMA1 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CR_INTR_EVENT = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CR_INTR_DMA2 = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CR_INTR_DMA3 = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CR_INTR_DMA4 = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CR_INTR_DMA5 = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CR_INTR_DMA6 = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CR_INTR_DMA7 = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CR_INTR_ALL_C = 0x0000003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CR_INTR_ALL_G = 0x000003ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CR_INTR_DMA_ALL = 0x000003f5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CR_INTR_ALL = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline int CR_INTR_DMA(int N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const unsigned int _CR_INTR_DMA[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return _CR_INTR_DMA[N];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum rsxx_pci_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DMA_QUEUE_RESET = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum rsxx_hw_fifo_flush {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RSXX_FLUSH_BUSY = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) RSXX_FLUSH_TIMEOUT = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum rsxx_pci_revision {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RSXX_DISCARD_SUPPORT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RSXX_EEH_SUPPORT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum rsxx_creg_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CREG_CMD_TAG_MASK = 0x0000FF00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CREG_OP_WRITE = 0x000000C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) CREG_OP_READ = 0x000000E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum rsxx_creg_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CREG_ADD_CARD_CMD = 0x80001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CREG_ADD_CARD_STATE = 0x80001004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CREG_ADD_CARD_SIZE = 0x8000100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CREG_ADD_CAPABILITIES = 0x80001050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) CREG_ADD_LOG = 0x80002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CREG_ADD_NUM_TARGETS = 0x80003000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CREG_ADD_CRAM = 0xA0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CREG_ADD_CONFIG = 0xB0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum rsxx_creg_card_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CARD_CMD_STARTUP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CARD_CMD_SHUTDOWN = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CARD_CMD_LOW_LEVEL_FORMAT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CARD_CMD_FPGA_RECONFIG_BR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CARD_CMD_FPGA_RECONFIG_MAIN = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CARD_CMD_BACKUP = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CARD_CMD_RESET = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CARD_CMD_deprecated = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CARD_CMD_UNINITIALIZE = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CARD_CMD_DSTROY_EMERGENCY = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CARD_CMD_DSTROY_NORMAL = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CARD_CMD_DSTROY_EXTENDED = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CARD_CMD_DSTROY_ABORT = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum rsxx_card_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CARD_STATE_SHUTDOWN = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CARD_STATE_STARTING = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CARD_STATE_FORMATTING = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CARD_STATE_UNINITIALIZED = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CARD_STATE_GOOD = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CARD_STATE_SHUTTING_DOWN = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CARD_STATE_FAULT = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CARD_STATE_RD_ONLY_FAULT = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CARD_STATE_DSTROYING = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum rsxx_led {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LED_DEFAULT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LED_IDENTIFY = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) LED_SOAK = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum rsxx_creg_flash_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CREG_FLASH_LOCK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CREG_FLASH_UNLOCK = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum rsxx_card_capabilities {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CARD_CAP_SUBPAGE_WRITES = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum rsxx_creg_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CREG_STAT_STATUS_MASK = 0x00000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CREG_STAT_SUCCESS = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CREG_STAT_ERROR = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CREG_STAT_CHAR_PENDING = 0x00000004, /* Character I/O pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CREG_STAT_LOG_PENDING = 0x00000008, /* HW log message pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CREG_STAT_TAG_MASK = 0x0000ff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) enum rsxx_dma_finish {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FREE_DMA = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) COMPLETE_DMA = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline unsigned int CREG_DATA(int N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return CREG_DATA0 + (N << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*----------------- Convenient Log Wrappers -------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CARD_TO_DEV(__CARD) (&(__CARD)->dev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /***** config.c *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int rsxx_load_config(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /***** core.c *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /***** dev.c *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int rsxx_attach_dev(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) void rsxx_detach_dev(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int rsxx_setup_dev(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void rsxx_destroy_dev(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int rsxx_dev_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void rsxx_dev_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /***** dma.c ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void *cb_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int rsxx_dma_setup(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void rsxx_dma_destroy(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int rsxx_dma_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct list_head *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void rsxx_dma_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int rsxx_dma_configure(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) blk_status_t rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct bio *bio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) atomic_t *n_dmas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rsxx_dma_cb cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void *cb_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /***** cregs.c *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int size8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int byte_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int rsxx_creg_read(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int size8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int byte_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int rsxx_read_hw_log(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int rsxx_get_card_state(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int rsxx_get_num_targets(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int *n_targets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 *capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int rsxx_creg_setup(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void rsxx_creg_destroy(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int rsxx_creg_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void rsxx_creg_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int rsxx_reg_access(struct rsxx_cardinfo *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct rsxx_reg_access __user *ucmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #endif /* __DRIVERS_BLOCK_RSXX_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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