^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ps3vram - Use extra PS3 video ram as block device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Sony Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the MTD ps3vram driver, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cell-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/lv1call.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/ps3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/ps3gpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DEVICE_NAME "ps3vram"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XDR_IOIF 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FIFO_BASE XDR_IOIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FIFO_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_PAGE_SIZE (4 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CACHE_PAGE_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CACHE_OFFSET CACHE_PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FIFO_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CTRL_PUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTRL_GET 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTRL_TOP 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UPLOAD_SUBCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DOWNLOAD_SUBCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CACHE_PAGE_PRESENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CACHE_PAGE_DIRTY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ps3vram_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ps3vram_cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ps3vram_tag *tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int hit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int miss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct ps3vram_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct request_queue *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct gendisk *gendisk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 memory_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u64 context_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *reports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 *xdr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 *fifo_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 *fifo_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ps3vram_cache cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spinlock_t lock; /* protecting list of bios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct bio_list list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int ps3vram_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DMA_NOTIFIER_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NOTIFIER 7 /* notifier used for completion report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static char *size = "256M";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_param(size, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_PARM_DESC(size, "memory size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return reports + DMA_NOTIFIER_OFFSET_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DMA_NOTIFIER_SIZE * notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) iowrite32be(0xffffffff, notify + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) for (timeout = 20; timeout; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!ioread32be(notify + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) timeout = jiffies + msecs_to_jiffies(timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!ioread32be(notify + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ioread32be(priv->ctrl + CTRL_TOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *(priv->fifo_ptr)++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* asking the HV for a blit will kick the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) priv->fifo_ptr = priv->fifo_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mutex_lock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * sizeof(u32), priv->ctrl + CTRL_PUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* asking the HV for a blit will kick the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FIFO_SIZE - 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_dbg(&dev->core, "FIFO full, rewinding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ps3vram_wait_ring(dev, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ps3vram_rewind_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mutex_unlock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void ps3vram_bind(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ps3vram_out_ring(priv, 0x31337303);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ps3vram_out_ring(priv, 0x3137c0de);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ps3vram_fire_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ps3vram_upload(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int src_offset, unsigned int dst_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int len, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ps3vram_begin_ring(priv, UPLOAD_SUBCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ps3vram_out_ring(priv, XDR_IOIF + src_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ps3vram_out_ring(priv, dst_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ps3vram_out_ring(priv, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ps3vram_out_ring(priv, (1 << 8) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ps3vram_notifier_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ps3vram_begin_ring(priv, UPLOAD_SUBCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ps3vram_fire_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ps3vram_notifier_wait(dev, 200) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int ps3vram_download(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int src_offset, unsigned int dst_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int len, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ps3vram_out_ring(priv, src_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ps3vram_out_ring(priv, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ps3vram_out_ring(priv, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ps3vram_out_ring(priv, (1 << 8) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ps3vram_notifier_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ps3vram_out_ring(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ps3vram_fire_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ps3vram_notifier_wait(dev, 200) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ps3vram_cache *cache = &priv->cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cache->tags[entry].address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cache->tags[entry].address, DMA_PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cache->page_size / DMA_PAGE_SIZE) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&dev->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) entry * cache->page_size, cache->tags[entry].address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cache->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ps3vram_cache *cache = &priv->cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ps3vram_download(dev, address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CACHE_OFFSET + entry * cache->page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DMA_PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cache->page_size / DMA_PAGE_SIZE) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&dev->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "Failed to download from 0x%x to 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) address, entry * cache->page_size, cache->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cache->tags[entry].address = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct ps3vram_cache *cache = &priv->cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(&dev->core, "FLUSH\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for (i = 0; i < cache->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ps3vram_cache_evict(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cache->tags[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) loff_t address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct ps3vram_cache *cache = &priv->cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) offset = (unsigned int) (address & (cache->page_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) base = (unsigned int) (address - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* fully associative check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = 0; i < cache->page_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cache->tags[i].address == base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cache->hit++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cache->tags[i].address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* choose a random entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) i = (jiffies + (counter++)) % cache->page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_dbg(&dev->core, "Using entry %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ps3vram_cache_evict(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ps3vram_cache_load(dev, i, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cache->miss++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) priv->cache.page_count = CACHE_PAGE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) priv->cache.page_size = CACHE_PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) priv->cache.tags = kcalloc(CACHE_PAGE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sizeof(struct ps3vram_tag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!priv->cache.tags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ps3vram_cache_flush(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) kfree(priv->cache.tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) size_t len, size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int cached, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (unsigned int)from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (from >= priv->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return BLK_STS_IOERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (len > priv->size - from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) len = priv->size - from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Copy from vram to buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) count = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int offset, avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) offset = (unsigned int) (from & (priv->cache.page_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) avail = priv->cache.page_size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) entry = ps3vram_cache_match(dev, from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "avail=%08x count=%08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (unsigned int)from, cached, offset, avail, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (avail > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) avail = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) memcpy(buf, priv->xdr_buf + cached, avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) buf += avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) count -= avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) from += avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) size_t len, size_t *retlen, const u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int cached, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (to >= priv->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return BLK_STS_IOERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (len > priv->size - to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) len = priv->size - to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Copy from buf to vram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) count = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int offset, avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) offset = (unsigned int) (to & (priv->cache.page_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) avail = priv->cache.page_size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) entry = ps3vram_cache_match(dev, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "avail=%08x count=%08x\n", __func__, (unsigned int)to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cached, offset, avail, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (avail > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) avail = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) memcpy(priv->xdr_buf + cached, buf, avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) buf += avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) count -= avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) to += avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int ps3vram_proc_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct ps3vram_priv *priv = m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void ps3vram_proc_init(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct proc_dir_entry *pde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pde = proc_create_single_data(DEVICE_NAME, 0444, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ps3vram_proc_show, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!pde)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_warn(&dev->core, "failed to create /proc entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct bio *bio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int write = bio_data_dir(bio) == WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const char *op = write ? "write" : "read";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) loff_t offset = bio->bi_iter.bi_sector << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) blk_status_t error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct bio_vec bvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct bvec_iter iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct bio *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) bio_for_each_segment(bvec, bio, iter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* PS3 is ppc64, so we don't handle highmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) char *ptr = page_address(bvec.bv_page) + bvec.bv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) size_t len = bvec.bv_len, retlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) len, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) error = ps3vram_write(dev, offset, len, &retlen, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) error = ps3vram_read(dev, offset, len, &retlen, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(&dev->core, "%s failed\n", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (retlen != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&dev->core, "Short %s\n", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) error = BLK_STS_IOERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) offset += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_dbg(&dev->core, "%s completed\n", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bio_list_pop(&priv->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) next = bio_list_peek(&priv->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bio->bi_status = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bio_endio(bio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static blk_qc_t ps3vram_submit_bio(struct bio *bio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct ps3_system_bus_device *dev = bio->bi_disk->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(&dev->core, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) blk_queue_split(&bio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) busy = !bio_list_empty(&priv->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) bio_list_add(&priv->list, bio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return BLK_QC_T_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bio = ps3vram_do_bio(dev, bio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } while (bio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return BLK_QC_T_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct block_device_operations ps3vram_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .submit_bio = ps3vram_submit_bio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int ps3vram_probe(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct ps3vram_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int error, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct request_queue *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct gendisk *gendisk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reports_size, xdr_lpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) char *rest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bio_list_init(&priv->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ps3_system_bus_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Allocate XDR buffer (1MiB aligned) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) get_order(XDR_BUF_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (priv->xdr_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(&dev->core, "Could not allocate XDR buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto fail_free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Put FIFO at begginning of XDR buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) priv->fifo_ptr = priv->fifo_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ps3_open_hv_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(&dev->core, "ps3_open_hv_device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) error = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) goto out_free_xdr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Request memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!ddr_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(&dev->core, "Specified size is too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto out_close_gpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) while (ddr_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &priv->memory_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &ddr_lpar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ddr_size -= 1024*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto out_close_gpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Request context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) status = lv1_gpu_context_allocate(priv->memory_handle, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &priv->context_handle, &ctrl_lpar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &info_lpar, &reports_lpar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &reports_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto out_free_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Map XDR buffer to RSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) xdr_lpar, XDR_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) CBE_IOPTE_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto out_free_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!priv->ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_err(&dev->core, "ioremap CTRL failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto out_unmap_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) priv->reports = ioremap(reports_lpar, reports_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!priv->reports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_err(&dev->core, "ioremap REPORTS failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto out_unmap_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mutex_lock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ps3vram_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mutex_unlock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) priv->size = ddr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ps3vram_bind(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_lock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) error = ps3vram_wait_ring(dev, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_unlock(&ps3_gpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(&dev->core, "Failed to initialize channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out_unmap_reports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) error = ps3vram_cache_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) goto out_unmap_reports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ps3vram_proc_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) queue = blk_alloc_queue(NUMA_NO_NODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(&dev->core, "blk_alloc_queue failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto out_cache_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) priv->queue = queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) blk_queue_max_segments(queue, BLK_MAX_SEGMENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) blk_queue_max_segment_size(queue, BLK_MAX_SEGMENT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) blk_queue_max_hw_sectors(queue, BLK_SAFE_MAX_SECTORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) gendisk = alloc_disk(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!gendisk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(&dev->core, "alloc_disk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto fail_cleanup_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) priv->gendisk = gendisk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) gendisk->major = ps3vram_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) gendisk->first_minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) gendisk->fops = &ps3vram_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gendisk->queue = queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) gendisk->private_data = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) set_capacity(gendisk, priv->size >> 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_info(&dev->core, "%s: Using %llu MiB of GPU memory\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) gendisk->disk_name, get_capacity(gendisk) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) device_add_disk(&dev->core, gendisk, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fail_cleanup_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) blk_cleanup_queue(queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) out_cache_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) remove_proc_entry(DEVICE_NAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ps3vram_cache_cleanup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) out_unmap_reports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) iounmap(priv->reports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) out_unmap_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) iounmap(priv->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) out_unmap_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) XDR_BUF_SIZE, CBE_IOPTE_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) out_free_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) lv1_gpu_context_free(priv->context_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) out_free_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) lv1_gpu_memory_free(priv->memory_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) out_close_gpu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ps3_close_hv_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) out_free_xdr_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) fail_free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ps3_system_bus_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int ps3vram_remove(struct ps3_system_bus_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) del_gendisk(priv->gendisk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) put_disk(priv->gendisk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) blk_cleanup_queue(priv->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) remove_proc_entry(DEVICE_NAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ps3vram_cache_cleanup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) iounmap(priv->reports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) iounmap(priv->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) XDR_BUF_SIZE, CBE_IOPTE_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) lv1_gpu_context_free(priv->context_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) lv1_gpu_memory_free(priv->memory_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ps3_close_hv_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ps3_system_bus_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct ps3_system_bus_driver ps3vram = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .match_id = PS3_MATCH_ID_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .core.name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .core.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .probe = ps3vram_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .remove = ps3vram_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .shutdown = ps3vram_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int __init ps3vram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) error = register_blkdev(0, DEVICE_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (error <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ps3vram_major = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pr_info("%s: registered block device major %d\n", DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ps3vram_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) error = ps3_system_bus_driver_register(&ps3vram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unregister_blkdev(ps3vram_major, DEVICE_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void __exit ps3vram_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ps3_system_bus_driver_unregister(&ps3vram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unregister_blkdev(ps3vram_major, DEVICE_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) module_init(ps3vram_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) module_exit(ps3vram_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MODULE_AUTHOR("Sony Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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