^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ppc6lnx.c (c) 2001 Micro Solutions Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Released under the terms of the GNU General Public license
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ppc6lnx.c is a par of the protocol driver for the Micro Solutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "BACKPACK" parallel port IDE adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) (Works on Series 6 drives)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // PPC 6 Code in C sanitized for LINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // Original x86 ASM by Ron, Converted to C by Clive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define port_stb 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define port_afd 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define cmd_stb port_afd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define port_init 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define data_stb port_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define port_sel 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define port_int 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define port_dir 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ECR_EPP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ECR_BI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) // 60772 Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACCESS_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACCESS_PORT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACCESS_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACCESS_WRITE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) // 60772 Command Prefix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_PREFIX_SET 0xe0 // Special command that modifies the next command's operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMD_PREFIX_RESET 0xc0 // Resets current cmd modifier reg bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PREFIX_IO16 0x01 // perform 16-bit wide I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PREFIX_FASTWR 0x04 // enable PPC mode fast-write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PREFIX_BLK 0x08 // enable block transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) // 60772 Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_STATUS 0x00 // status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STATUS_IRQA 0x01 // Peripheral IRQA line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STATUS_EEPROM_DO 0x40 // Serial EEPROM data bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_VERSION 0x01 // PPC version register (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_HWCFG 0x02 // Hardware Config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_RAMSIZE 0x03 // Size of RAM Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RAMSIZE_128K 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_EEPROM 0x06 // EEPROM control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EEPROM_SK 0x01 // eeprom SK bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EEPROM_DI 0x02 // eeprom DI bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EEPROM_CS 0x04 // eeprom CS bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EEPROM_EN 0x08 // eeprom output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_BLKSIZE 0x08 // Block transfer len (24 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) typedef struct ppc_storage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 lpt_addr; // LPT base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 ppc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 mode; // operating mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) // 0 = PPC Uni SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) // 1 = PPC Uni FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) // 2 = PPC Bi SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) // 3 = PPC Bi FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) // 4 = EPP Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) // 5 = EPP Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) // 6 = EPP Dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 ppc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 org_data; // original LPT data port contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 org_ctrl; // original LPT control port contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 cur_ctrl; // current control port contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } Interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) // ppc_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define fifo_wait 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) // DONT CHANGE THESE LEST YOU BREAK EVERYTHING - BIT FIELD DEPENDENCIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PPCMODE_UNI_SW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PPCMODE_UNI_FW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PPCMODE_BI_SW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PPCMODE_BI_FW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PPCMODE_EPP_BYTE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PPCMODE_EPP_WORD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PPCMODE_EPP_DWORD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ppc6_select(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void ppc6_deselect(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void ppc6_send_cmd(Interface *ppc, u8 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void ppc6_wr_data_byte(Interface *ppc, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u8 ppc6_rd_data_byte(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static u8 ppc6_rd_port(Interface *ppc, u8 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void ppc6_wr_port(Interface *ppc, u8 port, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void ppc6_rd_data_blk(Interface *ppc, u8 *data, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void ppc6_wait_for_fifo(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void ppc6_wr_data_blk(Interface *ppc, u8 *data, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void ppc6_rd_port16_blk(Interface *ppc, u8 port, u8 *data, long length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void ppc6_wr_port16_blk(Interface *ppc, u8 port, u8 *data, long length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void ppc6_wr_extout(Interface *ppc, u8 regdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int ppc6_open(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void ppc6_close(Interface *ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int ppc6_select(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 i, j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) i = inb(ppc->lpt_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (i & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) outb(i, ppc->lpt_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ppc->org_data = inb(ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ppc->org_ctrl = inb(ppc->lpt_addr + 2) & 0x5F; // readback ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ppc->cur_ctrl = ppc->org_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ppc->cur_ctrl |= port_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ppc->org_data == 'b')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb('x', ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) outb('b', ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) outb('p', ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) outb(ppc->ppc_id, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outb(~ppc->ppc_id,ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ppc->cur_ctrl &= ~port_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ppc->cur_ctrl = (ppc->cur_ctrl & port_int) | port_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) i = ppc->mode & 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) i = (ppc->mode & 2) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) outb(i, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ppc->cur_ctrl |= port_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ppc->cur_ctrl |= port_afd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) j = ((i & 0x08) << 4) | ((i & 0x07) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) k = inb(ppc->lpt_addr + 1) & 0xB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (j == k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ppc->cur_ctrl &= ~port_afd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) k = (inb(ppc->lpt_addr + 1) & 0xB8) ^ 0xB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (j == k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (i & 4) // EPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ppc->cur_ctrl &= ~(port_sel | port_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else // PPC/ECP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ppc->cur_ctrl &= ~port_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outb(ppc->org_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) outb(ppc->org_data, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return(0); // FAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void ppc6_deselect(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ppc->mode & 4) // EPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ppc->cur_ctrl |= port_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else // PPC/ECP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ppc->cur_ctrl |= port_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) outb(ppc->org_data, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) outb((ppc->org_ctrl | port_sel), ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) outb(ppc->org_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void ppc6_send_cmd(Interface *ppc, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch(ppc->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case PPCMODE_UNI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case PPCMODE_UNI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case PPCMODE_BI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case PPCMODE_BI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) outb(cmd, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ppc->cur_ctrl ^= cmd_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case PPCMODE_EPP_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case PPCMODE_EPP_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case PPCMODE_EPP_DWORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) outb(cmd, ppc->lpt_addr + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void ppc6_wr_data_byte(Interface *ppc, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch(ppc->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case PPCMODE_UNI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case PPCMODE_UNI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case PPCMODE_BI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case PPCMODE_BI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) outb(data, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ppc->cur_ctrl ^= data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case PPCMODE_EPP_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case PPCMODE_EPP_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case PPCMODE_EPP_DWORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) outb(data, ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static u8 ppc6_rd_data_byte(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) switch(ppc->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case PPCMODE_UNI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case PPCMODE_UNI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ppc->cur_ctrl = (ppc->cur_ctrl & ~port_stb) ^ data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) data = inb(ppc->lpt_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) data = ((data & 0x80) >> 1) | ((data & 0x38) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ppc->cur_ctrl |= port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) data |= inb(ppc->lpt_addr + 1) & 0xB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case PPCMODE_BI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case PPCMODE_BI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ppc->cur_ctrl |= port_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ppc->cur_ctrl = (ppc->cur_ctrl | port_stb) ^ data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) data = inb(ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ppc->cur_ctrl &= ~port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) outb(ppc->cur_ctrl,ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ppc->cur_ctrl &= ~port_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case PPCMODE_EPP_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case PPCMODE_EPP_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case PPCMODE_EPP_DWORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) outb((ppc->cur_ctrl | port_dir),ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data = inb(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) outb(ppc->cur_ctrl,ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static u8 ppc6_rd_port(Interface *ppc, u8 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ppc6_send_cmd(ppc,(u8)(port | ACCESS_PORT | ACCESS_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return(ppc6_rd_data_byte(ppc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void ppc6_wr_port(Interface *ppc, u8 port, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ppc6_send_cmd(ppc,(u8)(port | ACCESS_PORT | ACCESS_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ppc6_wr_data_byte(ppc, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void ppc6_rd_data_blk(Interface *ppc, u8 *data, long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch(ppc->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case PPCMODE_UNI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case PPCMODE_UNI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ppc->cur_ctrl = (ppc->cur_ctrl & ~port_stb) ^ data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) d = inb(ppc->lpt_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) d = ((d & 0x80) >> 1) | ((d & 0x38) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ppc->cur_ctrl |= port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) d |= inb(ppc->lpt_addr + 1) & 0xB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *data++ = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case PPCMODE_BI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case PPCMODE_BI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ppc->cur_ctrl |= port_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ppc->cur_ctrl |= port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ppc->cur_ctrl ^= data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *data++ = inb(ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ppc->cur_ctrl &= ~port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ppc->cur_ctrl &= ~port_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case PPCMODE_EPP_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) outb((ppc->cur_ctrl | port_dir), ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *data++ = inb(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case PPCMODE_EPP_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) outb((ppc->cur_ctrl | port_dir), ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) while(count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *((u16 *)data) = inw(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *data++ = inb(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case PPCMODE_EPP_DWORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) outb((ppc->cur_ctrl | port_dir),ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) // DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) while(count > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *((u32 *)data) = inl(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) data += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) count -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *data++ = inb(ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void ppc6_wait_for_fifo(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ppc->ppc_flags & fifo_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for(i=0; i<20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) inb(ppc->lpt_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void ppc6_wr_data_blk(Interface *ppc, u8 *data, long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch(ppc->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case PPCMODE_UNI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case PPCMODE_BI_SW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) while(count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) outb(*data++, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ppc->cur_ctrl ^= data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case PPCMODE_UNI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case PPCMODE_BI_FW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u8 this, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ppc6_send_cmd(ppc,(CMD_PREFIX_SET | PREFIX_FASTWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ppc->cur_ctrl |= port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) last = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) outb(last, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) this = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (this == last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ppc->cur_ctrl ^= data_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) outb(this, ppc->lpt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) last = this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ppc->cur_ctrl &= ~port_stb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) outb(ppc->cur_ctrl, ppc->lpt_addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ppc6_send_cmd(ppc,(CMD_PREFIX_RESET | PREFIX_FASTWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case PPCMODE_EPP_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) outb(*data++,ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ppc6_wait_for_fifo(ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case PPCMODE_EPP_WORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while(count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) outw(*((u16 *)data),ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) outb(*data++,ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ppc6_wait_for_fifo(ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case PPCMODE_EPP_DWORD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) while(count > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) outl(*((u32 *)data),ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) data += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) count -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) while(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) outb(*data++,ppc->lpt_addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ppc6_wait_for_fifo(ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void ppc6_rd_port16_blk(Interface *ppc, u8 port, u8 *data, long length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) length = length << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ppc6_send_cmd(ppc, (REG_BLKSIZE | ACCESS_REG | ACCESS_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ppc6_wr_data_byte(ppc,(u8)length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ppc6_wr_data_byte(ppc,(u8)(length >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ppc6_wr_data_byte(ppc,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ppc6_send_cmd(ppc, (CMD_PREFIX_SET | PREFIX_IO16 | PREFIX_BLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ppc6_send_cmd(ppc, (u8)(port | ACCESS_PORT | ACCESS_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ppc6_rd_data_blk(ppc, data, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ppc6_send_cmd(ppc, (CMD_PREFIX_RESET | PREFIX_IO16 | PREFIX_BLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void ppc6_wr_port16_blk(Interface *ppc, u8 port, u8 *data, long length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) length = length << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ppc6_send_cmd(ppc, (REG_BLKSIZE | ACCESS_REG | ACCESS_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ppc6_wr_data_byte(ppc,(u8)length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ppc6_wr_data_byte(ppc,(u8)(length >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ppc6_wr_data_byte(ppc,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ppc6_send_cmd(ppc, (CMD_PREFIX_SET | PREFIX_IO16 | PREFIX_BLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ppc6_send_cmd(ppc, (u8)(port | ACCESS_PORT | ACCESS_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ppc6_wr_data_blk(ppc, data, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ppc6_send_cmd(ppc, (CMD_PREFIX_RESET | PREFIX_IO16 | PREFIX_BLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void ppc6_wr_extout(Interface *ppc, u8 regdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ppc6_send_cmd(ppc,(REG_VERSION | ACCESS_REG | ACCESS_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ppc6_wr_data_byte(ppc, (u8)((regdata & 0x03) << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int ppc6_open(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = ppc6_select(ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ppc->ppc_flags &= ~fifo_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ppc6_send_cmd(ppc, (ACCESS_REG | ACCESS_WRITE | REG_RAMSIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ppc6_wr_data_byte(ppc, RAMSIZE_128K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ppc6_send_cmd(ppc, (ACCESS_REG | ACCESS_READ | REG_VERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if ((ppc6_rd_data_byte(ppc) & 0x3F) == 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ppc->ppc_flags |= fifo_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void ppc6_close(Interface *ppc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ppc6_deselect(ppc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) //***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags