^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef __DRIVERS_PARIDE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define __DRIVERS_PARIDE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) paride.h (c) 1997-8 Grant R. Guenther <grant@torque.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Under the terms of the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This file defines the interface between the high-level parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) IDE device drivers (pd, pf, pcd, pt) and the adapter chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 1.01 GRG 1998.05.05 init_proto, release_proto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PARIDE_H_VERSION "1.01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Some adapters need to know what kind of device they are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Values for devtype:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PI_PD 0 /* IDE disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PI_PCD 1 /* ATAPI CDrom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PI_PF 2 /* ATAPI disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PI_PT 3 /* ATAPI tape */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PI_PG 4 /* ATAPI generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* The paride module contains no state, instead the drivers allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) a pi_adapter data structure and pass it to paride in every operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pi_adapter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pi_protocol *proto; /* adapter protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int port; /* base address of parallel port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int mode; /* transfer mode in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int delay; /* adapter delay setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int devtype; /* device type: PI_PD etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) char *device; /* name of driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int unit; /* unit number for chained adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int saved_r0; /* saved port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int saved_r2; /* saved port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int reserved; /* number of ports reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long private; /* for protocol module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) wait_queue_head_t parq; /* semaphore for parport sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void *pardev; /* pointer to pardevice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) char *parname; /* parport name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int claimed; /* parport has already been claimed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void (*claim_cont)(void); /* continuation for parport wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) typedef struct pi_adapter PIA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* functions exported by paride to the high level drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern int pi_init(PIA *pi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int autoprobe, /* 1 to autoprobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int port, /* base port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int mode, /* -1 for autoprobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int unit, /* unit number, if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int protocol, /* protocol to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int delay, /* -1 to use adapter specific default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) char * scratch, /* address of 512 byte buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int devtype, /* device type: PI_PD, PI_PCD, etc ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int verbose, /* log verbose data while probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char *device /* name of the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ); /* returns 0 on failure, 1 on success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern void pi_release(PIA *pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* registers are addressed as (cont,regr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cont: 0 for command register file, 1 for control register(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regr: 0-7 for register number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern void pi_write_regr(PIA *pi, int cont, int regr, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int pi_read_regr(PIA *pi, int cont, int regr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern void pi_write_block(PIA *pi, char * buf, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern void pi_read_block(PIA *pi, char * buf, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern void pi_connect(PIA *pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern void pi_disconnect(PIA *pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern void pi_do_claimed(PIA *pi, void (*cont)(void));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern int pi_schedule_claimed(PIA *pi, void (*cont)(void));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* macros and functions exported to the protocol modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define delay_p (pi->delay?udelay(pi->delay):(void)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define out_p(offs,byte) outb(byte,pi->port+offs); delay_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define in_p(offs) (delay_p,inb(pi->port+offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define w0(byte) {out_p(0,byte);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define r0() (in_p(0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define w1(byte) {out_p(1,byte);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define r1() (in_p(1) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define w2(byte) {out_p(2,byte);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define r2() (in_p(2) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define w3(byte) {out_p(3,byte);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define w4(byte) {out_p(4,byte);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define r4() (in_p(4) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define w4w(data) {outw(data,pi->port+4); delay_p;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define w4l(data) {outl(data,pi->port+4); delay_p;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define r4w() (delay_p,inw(pi->port+4)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define r4l() (delay_p,inl(pi->port+4)&0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline u16 pi_swab16( char *b, int k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { union { u16 u; char t[2]; } r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) r.t[0]=b[2*k+1]; r.t[1]=b[2*k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return r.u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline u32 pi_swab32( char *b, int k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { union { u32 u; char f[4]; } r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) r.f[0]=b[4*k+1]; r.f[1]=b[4*k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) r.f[2]=b[4*k+3]; r.f[3]=b[4*k+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return r.u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pi_protocol {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) char name[8]; /* name for this protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int index; /* index into protocol table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int max_mode; /* max mode number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int epp_first; /* modes >= this use 8 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int default_delay; /* delay parameter if not specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int max_units; /* max chained units probed for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void (*write_regr)(PIA *,int,int,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int (*read_regr)(PIA *,int,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void (*write_block)(PIA *,char *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void (*read_block)(PIA *,char *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void (*connect)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void (*disconnect)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int (*test_port)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int (*probe_unit)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int (*test_proto)(PIA *,char *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void (*log_adapter)(PIA *,char *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int (*init_proto)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void (*release_proto)(PIA *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) typedef struct pi_protocol PIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) extern int paride_register( PIP * );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern void paride_unregister ( PIP * );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void *pi_register_driver(char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void pi_unregister_driver(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif /* __DRIVERS_PARIDE_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* end of paride.h */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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