^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mtip32xx.h - Header file for the P320 SSD Block Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Micron Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Portions of this code were derived from works subjected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * following copyright:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __MTIP32XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __MTIP32XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rwsem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/genhd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Offset of Subsystem Device ID in pci confoguration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_SUBSYSTEM_DEVICEID 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* offset of Device Control register in PCIe extended capabilites space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* check for erase mode support during secure erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MTIP_SEC_ERASE_MODE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* # of times to retry timed out/failed IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MTIP_MAX_RETRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Various timeout values in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MTIP_NCQ_CMD_TIMEOUT_MS 15000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MTIP_IOCTL_CMD_TIMEOUT_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MTIP_INT_CMD_TIMEOUT_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MTIP_QUIESCE_IO_TIMEOUT_MS (MTIP_NCQ_CMD_TIMEOUT_MS * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (MTIP_MAX_RETRIES + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* check for timeouts every 500ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MTIP_TIMEOUT_CHECK_PERIOD 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ftl rebuild */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MTIP_FTL_REBUILD_OFFSET 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MTIP_FTL_REBUILD_MAGIC 0xED51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTIP_FTL_REBUILD_TIMEOUT_MS 2400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* unaligned IO handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MTIP_MAX_UNALIGNED_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Macro to extract the tag bit number from a tag value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MTIP_TAG_BIT(tag) (tag & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Macro to extract the tag index from a tag value. The index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * is used to access the correct s_active/Command Issue register based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * on the tag value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MTIP_TAG_INDEX(tag) (tag >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Maximum number of scatter gather entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * a single command may have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MTIP_MAX_SG 504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Maximum number of slot groups (Command Issue & s_active registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * NOTE: This is the driver maximum; check dd->slot_groups for actual value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MTIP_MAX_SLOT_GROUPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Internal command tag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MTIP_TAG_INTERNAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Micron Vendor ID & P320x SSD Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_VENDOR_ID_MICRON 0x1344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define P320H_DEVICE_ID 0x5150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define P320M_DEVICE_ID 0x5151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define P320S_DEVICE_ID 0x5152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define P325M_DEVICE_ID 0x5153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define P420H_DEVICE_ID 0x5160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define P420M_DEVICE_ID 0x5161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define P425M_DEVICE_ID 0x5163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Driver name and version strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MTIP_DRV_NAME "mtip32xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MTIP_DRV_VERSION "1.3.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Maximum number of minor device numbers per device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MTIP_MAX_MINORS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Maximum number of supported command slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MTIP_MAX_COMMAND_SLOTS (MTIP_MAX_SLOT_GROUPS * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Per-tag bitfield size in longs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Linux bit manipulation functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * (i.e. test_and_set_bit, find_next_zero_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * manipulate memory in longs, so we try to make the math work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * take the slot groups and find the number of longs, rounding up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Careful! i386 and x86_64 use different size longs!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define U32_PER_LONG (sizeof(long) / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLOTBITS_IN_LONGS ((MTIP_MAX_SLOT_GROUPS + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (U32_PER_LONG-1))/U32_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* BAR number used to access the HBA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MTIP_ABAR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define dbg_printk(format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) printk(pr_fmt(format), ##arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define dbg_printk(format, arg...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MTIP_DFS_MAX_BUF_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* below are bit numbers in 'flags' defined in mtip_port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MTIP_PF_IC_ACTIVE_BIT = 0, /* pio/ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MTIP_PF_EH_ACTIVE_BIT = 1, /* error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MTIP_PF_SE_ACTIVE_BIT = 2, /* secure erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MTIP_PF_DM_ACTIVE_BIT = 3, /* download microcde */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MTIP_PF_TO_ACTIVE_BIT = 9, /* timeout handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTIP_PF_PAUSE_IO = ((1 << MTIP_PF_IC_ACTIVE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (1 << MTIP_PF_EH_ACTIVE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) (1 << MTIP_PF_SE_ACTIVE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (1 << MTIP_PF_DM_ACTIVE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (1 << MTIP_PF_TO_ACTIVE_BIT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTIP_PF_HOST_CAP_64 = 10, /* cache HOST_CAP_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTIP_PF_ISSUE_CMDS_BIT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MTIP_PF_REBUILD_BIT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTIP_PF_SVC_THD_STOP_BIT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTIP_PF_SVC_THD_WORK = ((1 << MTIP_PF_EH_ACTIVE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (1 << MTIP_PF_ISSUE_CMDS_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (1 << MTIP_PF_REBUILD_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (1 << MTIP_PF_SVC_THD_STOP_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (1 << MTIP_PF_TO_ACTIVE_BIT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* below are bit numbers in 'dd_flag' defined in driver_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MTIP_DDF_SEC_LOCK_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MTIP_DDF_REMOVE_PENDING_BIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTIP_DDF_OVER_TEMP_BIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MTIP_DDF_WRITE_PROTECT_BIT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTIP_DDF_CLEANUP_BIT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTIP_DDF_RESUME_BIT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTIP_DDF_INIT_DONE_BIT = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTIP_DDF_REBUILD_FAILED_BIT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MTIP_DDF_REMOVAL_BIT = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTIP_DDF_STOP_IO = ((1 << MTIP_DDF_REMOVE_PENDING_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (1 << MTIP_DDF_SEC_LOCK_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (1 << MTIP_DDF_OVER_TEMP_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (1 << MTIP_DDF_WRITE_PROTECT_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (1 << MTIP_DDF_REBUILD_FAILED_BIT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct smart_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 attr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 worst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __le32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 res[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct mtip_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int cpu_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } ____cacheline_aligned_in_smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DEFINE_HANDLER(group) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void mtip_workq_sdbf##group(struct work_struct *work) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct mtip_work *w = (struct mtip_work *) work; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mtip_workq_sdbfx(w->port, group, w->completed); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Register Frame Information Structure (FIS), host to device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct host_to_dev_fis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * FIS type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * - 27h Register FIS, host to device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * - 34h Register FIS, device to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * - 39h DMA Activate FIS, device to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - 41h DMA Setup FIS, bi-directional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * - 46h Data FIS, bi-directional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * - 58h BIST Activate FIS, bi-directional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * - 5Fh PIO Setup FIS, device to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * - A1h Set Device Bits FIS, device to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned char type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned char opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned char lba_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char sector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned char lba_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char cyl_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned char lba_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned char cyl_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned char lba_low_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char sector_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned char lba_mid_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char cyl_low_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char lba_hi_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned char cyl_hi_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned char features_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char sect_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned char sect_cnt_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned char res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned char control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Command header structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mtip_cmd_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Command options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * - Bits 31:16 Number of PRD entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * - Bits 15:8 Unused in this implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * - Bit 7 Prefetch bit, informs the drive to prefetch PRD entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * - Bit 6 Write bit, should be set when writing data to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * - Bit 5 Unused in this implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * - Bits 4:0 Length of the command FIS in DWords (DWord = 4 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __le32 opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* This field is unsed when using NCQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __le32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Lower 32 bits of the command table address associated with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * header. The command table addresses must be 128 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le32 ctba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * If 64 bit addressing is used this field is the upper 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * of the command table address associated with this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __le32 ctbau;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Reserved and unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 res[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Command scatter gather structure (PRD). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct mtip_cmd_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Low 32 bits of the data buffer address. For P320 this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * address must be 8 byte aligned signified by bits 2:0 being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le32 dba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * When 64 bit addressing is used this field is the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 32 bits of the data buffer address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 dba_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Bit 31: interrupt when this data block has been transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Bits 30..22: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Bits 21..0: byte count (minus 1). For P320 the byte count must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * 8 byte aligned signified by bits 2:0 being set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __le32 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct mtip_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct mtip_int_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Structure used to describe a command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mtip_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void *command; /* ptr to command table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dma_addr_t command_dma; /* corresponding physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int scatter_ents; /* Number of scatter list entries used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int unaligned; /* command is unaligned on 4k boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct scatterlist sg[MTIP_MAX_SG]; /* Scatter list entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mtip_int_cmd *icmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int retries; /* The number of retries left for this command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int direction; /* Data transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) blk_status_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Structure used to describe a port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct mtip_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Pointer back to the driver data for this port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct driver_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Used to determine if the data pointed to by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * identify field is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long identify_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Base address of the memory mapped IO for the port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Array of pointers to the memory mapped s_active registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void __iomem *s_active[MTIP_MAX_SLOT_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Array of pointers to the memory mapped completed registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void __iomem *completed[MTIP_MAX_SLOT_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Array of pointers to the memory mapped Command Issue registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void __iomem *cmd_issue[MTIP_MAX_SLOT_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Pointer to the beginning of the command header memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void *command_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Pointer to the beginning of the command header memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * by the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dma_addr_t command_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Pointer to the beginning of the RX FIS memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void *rxfis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Pointer to the beginning of the RX FIS memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * by the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dma_addr_t rxfis_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Pointer to the DMA region for RX Fis, Identify, RLE10, and SMART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void *block1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * DMA address of region for RX Fis, Identify, RLE10, and SMART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dma_addr_t block1_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Pointer to the beginning of the identify data memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u16 *identify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Pointer to the beginning of the identify data memory as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * by the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dma_addr_t identify_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Pointer to the beginning of a sector buffer that is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * by the driver when issuing internal commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 *sector_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Pointer to the beginning of a sector buffer that is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * by the DMA when the driver issues internal commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dma_addr_t sector_buffer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u16 *log_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dma_addr_t log_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 *smart_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dma_addr_t smart_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * used to queue commands when an internal command is in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * or error handling is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long cmds_to_issue[SLOTBITS_IN_LONGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Used by mtip_service_thread to wait for an event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) wait_queue_head_t svc_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * indicates the state of the port. Also, helps the service thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * to determine its action on wake up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Timer used to complete commands that have been active for too long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long ic_pause_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Counter to control queue depth of unaligned IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) atomic_t cmd_slot_unal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Spinlock for working around command-issue bug. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spinlock_t cmd_issue_lock[MTIP_MAX_SLOT_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Driver private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * One structure is allocated per probed device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void __iomem *mmio; /* Base address of the HBA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int major; /* Major device number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int instance; /* Instance number. First device probed is 0, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct gendisk *disk; /* Pointer to our gendisk structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct pci_dev *pdev; /* Pointer to the PCI device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct request_queue *queue; /* Our request queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct blk_mq_tag_set tags; /* blk_mq tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct mtip_port *port; /* Pointer to the port data structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned product_type; /* magic value declaring the product type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned slot_groups; /* number of slot groups the product supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long index; /* Index to determine the disk name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long dd_flag; /* NOTE: use atomic bit operations on this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct task_struct *mtip_svc_handler; /* task_struct of svc thd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct dentry *dfs_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bool sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int numa_node; /* NUMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) char workq_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct workqueue_struct *isr_workq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) atomic_t irq_workers_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mtip_work work[MTIP_MAX_SLOT_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int isr_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct block_device *bdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct list_head online_list; /* linkage for online list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct list_head remove_list; /* linkage for removing list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int unal_qdepth; /* qdepth of unaligned IO queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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