^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void bcma_host_pci_switch_core(struct bcma_device *core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int win2 = core->bus->host_is_pcie2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) BCMA_PCIE2_BAR0_WIN2 : BCMA_PCI_BAR0_WIN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) core->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pci_write_config_dword(core->bus->host_pci, win2, core->wrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) core->bus->mapped_core = core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Provides access to the requested core. Returns base offset that has to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * used. It makes use of fixed windows when possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) switch (core->id.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case BCMA_CORE_CHIPCOMMON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return 3 * BCMA_CORE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case BCMA_CORE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 2 * BCMA_CORE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (core->bus->mapped_core != core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bcma_host_pci_switch_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return ioread8(core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return ioread16(core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ioread32(core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) iowrite8(value, core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) iowrite16(value, core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) offset += bcma_host_pci_provide_access_to_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) iowrite32(value, core->bus->mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #ifdef CONFIG_BCMA_BLOCKIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) size_t count, u16 offset, u8 reg_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *addr = core->bus->mmio + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (core->bus->mapped_core != core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bcma_host_pci_switch_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (reg_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case sizeof(u8):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ioread8_rep(addr, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case sizeof(u16):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) WARN_ON(count & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ioread16_rep(addr, buffer, count >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case sizeof(u32):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) WARN_ON(count & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ioread32_rep(addr, buffer, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void bcma_host_pci_block_write(struct bcma_device *core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const void *buffer, size_t count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 offset, u8 reg_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *addr = core->bus->mmio + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (core->bus->mapped_core != core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bcma_host_pci_switch_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (reg_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case sizeof(u8):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iowrite8_rep(addr, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case sizeof(u16):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) WARN_ON(count & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) iowrite16_rep(addr, buffer, count >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case sizeof(u32):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) WARN_ON(count & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite32_rep(addr, buffer, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (core->bus->mapped_core != core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bcma_host_pci_switch_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (core->bus->mapped_core != core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bcma_host_pci_switch_core(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct bcma_host_ops bcma_host_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .read8 = bcma_host_pci_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .read16 = bcma_host_pci_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .read32 = bcma_host_pci_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .write8 = bcma_host_pci_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .write16 = bcma_host_pci_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .write32 = bcma_host_pci_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifdef CONFIG_BCMA_BLOCKIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .block_read = bcma_host_pci_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .block_write = bcma_host_pci_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .aread32 = bcma_host_pci_aread32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .awrite32 = bcma_host_pci_awrite32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int bcma_host_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct bcma_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Alloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bus = kzalloc(sizeof(*bus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Basic PCI configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto err_kfree_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) name = dev_name(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (dev->driver && dev->driver->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) name = dev->driver->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err = pci_request_regions(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto err_pci_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Disable the RETRY_TIMEOUT register (0x41) to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * PCI Tx retries from interfering with C3 CPU state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_read_config_dword(dev, 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((val & 0x0000ff00) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* SSB needed additional powering up, do we have any AMBA PCI cards? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!pci_is_pcie(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bcma_err(bus, "PCI card detected, they are not supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err_pci_release_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bus->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Map MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bus->mmio = pci_iomap(dev, 0, ~0UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!bus->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto err_pci_release_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Host specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bus->host_pci = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bus->hosttype = BCMA_HOSTTYPE_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bus->ops = &bcma_host_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bus->boardinfo.type = bus->host_pci->subsystem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Initialize struct, detect chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bcma_init_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Scan bus to find out generation of PCIe core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err = bcma_bus_scan(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto err_pci_unmap_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (bcma_find_core(bus, BCMA_CORE_PCIE2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bus->host_is_pcie2 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) err = bcma_bus_register(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto err_unregister_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pci_set_drvdata(dev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err_unregister_cores:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bcma_unregister_cores(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err_pci_unmap_mmio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_iounmap(dev, bus->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err_pci_release_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err_pci_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err_kfree_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) kfree(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void bcma_host_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct bcma_bus *bus = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bcma_bus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_iounmap(dev, bus->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) kfree(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int bcma_host_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct bcma_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bus->mapped_core = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return bcma_bus_suspend(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int bcma_host_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct bcma_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return bcma_bus_resume(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bcma_host_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BCMA_PM_OPS (&bcma_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #else /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BCMA_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct pci_device_id bcma_pci_bridge_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_FOXCONN, 0xe092) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_HP, 0x804a) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43b1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct pci_driver bcma_pci_bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "bcma-pci-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .id_table = bcma_pci_bridge_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .probe = bcma_host_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .remove = bcma_host_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .driver.pm = BCMA_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int __init bcma_host_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return pci_register_driver(&bcma_pci_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void __exit bcma_host_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pci_unregister_driver(&bcma_pci_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Runtime ops for drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* See also pcicore_up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void bcma_host_pci_up(struct bcma_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (bus->hosttype != BCMA_HOSTTYPE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (bus->host_is_pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcma_core_pcie2_up(&bus->drv_pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bcma_core_pci_up(&bus->drv_pci[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EXPORT_SYMBOL_GPL(bcma_host_pci_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* See also pcicore_down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void bcma_host_pci_down(struct bcma_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (bus->hosttype != BCMA_HOSTTYPE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!bus->host_is_pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bcma_core_pci_down(&bus->drv_pci[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) EXPORT_SYMBOL_GPL(bcma_host_pci_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* See also si_pci_setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 coremask, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (bus->hosttype != BCMA_HOSTTYPE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* This bcma device is not on a PCI host-bus. So the IRQs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * not routed through the PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * So we must not enable routing through the PCI core. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pdev = bus->host_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) coremask = BIT(core->core_index) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tmp |= coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tmp &= ~coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags