^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe Gen 2 Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * R/W ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* restore back to default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val |= PCIE2_CLKC_DLYPERST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) val &= ~PCIE2_CLKC_DISSPROMLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val &= ~PCIE2_CLKC_DLYPERST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) val |= PCIE2_CLKC_DISSPROMLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* LTR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* LTR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* LTR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 core_rev = pcie2->core->id.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 devstsctr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (core_rev < 2 || core_rev == 10 || core_rev > 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PCIE2_CAP_DEVSTSCTRL2_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* force the right LTR values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bcma_core_pcie2_set_ltr_vals(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* enable the LTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PCIE2_CAP_DEVSTSCTRL2_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* set the LTR state to be active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PCIE2_LTR_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* set the LTR state to be sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PCIE2_LTR_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 core_rev = pcie2->core->id.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool pciewar160, pciewar162;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) core_rev == 9 || core_rev == 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!pciewar160 && !pciewar162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PCIE_DISABLE_L1CLK_GATING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PCIEGEN2_COE_PVT_TL_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 core_rev = pcie2->core->id.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 alp_khz, pm_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (core_rev <= 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pm_value = (1000000 * 2) / alp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PCIE2_PVT_REG_PM_CLK_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct bcma_bus *bus = pcie2->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct bcma_chipinfo *ci = &bus->chipinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if ((tmp & 0xe) >> 1 == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case BCMA_CHIP_ID_BCM4360:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case BCMA_CHIP_ID_BCM4352:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pcie2->reqsize = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pcie2->reqsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bcma_core_pcie2_hw_ltr_war(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pciedev_crwlpciegen2(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pciedev_reg_pm_clk_period(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pciedev_crwlpciegen2_180(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pciedev_crwlpciegen2_182(pcie2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Runtime ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct bcma_bus *bus = pcie2->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct pci_dev *dev = bus->host_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = pcie_set_readrq(dev, pcie2->reqsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bcma_err(bus, "Error setting PCI_EXP_DEVCTL_READRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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