^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Core in hostmode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005 - 2011, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/paccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Probe a 32bit value on the bus and catch bus exceptions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Returns nonzero on a bus exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * This is MIPS specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Assume one-hot slot wiring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BCMA_PCI_SLOT_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_CONFIG_SPACE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct bcma_bus *bus = pc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 chipid_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) chipid_top = (bus->chipinfo.id & 0xFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (chipid_top != 0x4700 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) chipid_top != 0x5300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bcma_core_enable(pc->core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return !mips_busprobe32(tmp, pc->core->io_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int func, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Issue config commands only when the data link is up (atleast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * one external pcie device is present).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Type 0 transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Slide the PCI window to the appropriate slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Calculate the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) addr = pc->host_controller->host_cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) addr |= (off & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int func, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *mmio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) WARN_ON(!pc->hostmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (unlikely(len != 1 && len != 2 && len != 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (dev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* we support only two functions on device 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (func > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* accesses to config registers with offsets >= 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * requires indirect access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (off >= PCI_CONFIG_SPACE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) addr = (func << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) addr |= (off & 0x0FFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val = bcma_pcie_read_config(pc, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) addr = BCMA_CORE_PCI_PCICFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) addr |= (func << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) addr |= (off & 0xFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val = pcicore_read32(pc, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) addr = bcma_get_cfgspace_addr(pc, dev, func, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (unlikely(!addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mmio = ioremap(addr, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (mips_busprobe32(val, mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val >>= (8 * (off & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *((u8 *)buf) = (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *((u16 *)buf) = (u16)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *((u32 *)buf) = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iounmap(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int func, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const void *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *mmio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 chipid = pc->core->bus->chipinfo.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) WARN_ON(!pc->hostmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (unlikely(len != 1 && len != 2 && len != 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (dev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* we support only two functions on device 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (func > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* accesses to config registers with offsets >= 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * requires indirect access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (off >= PCI_CONFIG_SPACE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) addr = (func << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) addr |= (off & 0x0FFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = bcma_pcie_read_config(pc, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) addr = BCMA_CORE_PCI_PCICFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) addr |= (func << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) addr |= (off & 0xFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val = pcicore_read32(pc, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) addr = bcma_get_cfgspace_addr(pc, dev, func, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (unlikely(!addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mmio = ioremap(addr, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (mips_busprobe32(val, mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val &= ~(0xFF << (8 * (off & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val |= *((const u8 *)buf) << (8 * (off & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val &= ~(0xFFFF << (8 * (off & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val |= *((const u16 *)buf) << (8 * (off & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = *((const u32 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (dev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* accesses to config registers with offsets >= 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * requires indirect access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (off >= PCI_CONFIG_SPACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bcma_pcie_write_config(pc, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pcicore_write32(pc, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(val, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (chipid == BCMA_CHIP_ID_BCM4716 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) chipid == BCMA_CHIP_ID_BCM4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) readl(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) iounmap(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int reg, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct bcma_drv_pci *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct bcma_drv_pci_host *pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pc = pc_host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PCI_FUNC(devfn), reg, val, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int reg, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct bcma_drv_pci *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct bcma_drv_pci_host *pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pc = pc_host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PCI_FUNC(devfn), reg, &val, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* return cap_offset if requested capability exists in the PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int func, u8 req_cap_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char *buf, u32 *buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 cap_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 cap_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 byte_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* check for Header type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* check if the capability pointer field exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!(byte_val & PCI_STATUS_CAP_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* check if the capability pointer is 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (cap_ptr == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* loop thr'u the capability list and see if the requested capabilty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) while (cap_id != req_cap_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (cap_ptr == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* found the caller requested capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if ((buf != NULL) && (buflen != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 cap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bufsize = *buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *buflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* copy the cpability data excluding cap ID and next ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cap_data = cap_ptr + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *buflen = bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (bufsize--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bcma_extpci_read_config(pc, dev, func, cap_data, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cap_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* If the root port is capable of returning Config Request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Retry Status (CRS) Completion Status to software then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * enable the feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct bcma_bus *bus = pc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 cap_ptr, root_ctrl, root_cap, dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) root_cap = cap_ptr + PCI_EXP_RTCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Enable CRS software visibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) root_ctrl = cap_ptr + PCI_EXP_RTCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val16 = PCI_EXP_RTCTL_CRSSVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Initiate a configuration request to read the vendor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * field of the device function's config space header after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * 100 ms wait time from the end of Reset. If the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * not done with its internal initialization, it must at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * least return a completion TLP, with a completion status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * of "Configuration Request Retry Status (CRS)". The root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * complex must complete the request to the host by returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * a read-data value of 0001h for the Vendor ID field and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * all 1s for any additional bytes included in the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Poll using the config reads for max wait time of 1 sec or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * until we receive the successful completion status. Repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * the procedure for all the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < 100000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bcma_extpci_read_config(pc, dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PCI_VENDOR_ID, &val16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sizeof(val16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (val16 != 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (val16 == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bcma_err(bus, "PCI: Broken device in slot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct bcma_bus *bus = pc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct bcma_drv_pci_host *pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 pci_membase_1G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bcma_info(bus, "PCIEcore in host mode found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bcma_info(bus, "This PCIE core is disabled and not working\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!pc_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) bcma_err(bus, "can not allocate memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spin_lock_init(&pc_host->cfgspace_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pc->host_controller = pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pc_host->pci_controller.io_resource = &pc_host->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pc_host->pdev = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_membase_1G = BCMA_SOC_PCI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pc_host->mem_resource.name = "BCMA PCIcore external memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pc_host->io_resource.name = "BCMA PCIcore external I/O";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pc_host->io_resource.start = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pc_host->io_resource.end = 0x7FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Reset RC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BCMA_CORE_PCI_CTL_RST_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* 64 MB I/O access window. On 4716, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * sbtopcie0 to access the device registers. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * can't use address match 2 (1 GB window) region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * as mips can't generate 64-bit address on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * backplane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) BCMA_SOC_PCI_MEM_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (pc->core->core_unit == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BCMA_SOC_PCI_MEM_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pc_host->io_resource.start = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pc_host->io_resource.end = 0x47F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmp | BCMA_SOC_PCI_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else if (pc->core->core_unit == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BCMA_SOC_PCI_MEM_SZ - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pc_host->io_resource.start = 0x480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pc_host->io_resource.end = 0x7FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tmp | BCMA_SOC_PCI1_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BCMA_CORE_PCI_SBTOPCI_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* 64 MB configuration access window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* 1 GB memory access window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* As per PCI Express Base Spec 1.1 we need to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * at least 100 ms from the end of a reset (cold/warm/hot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * before issuing configuration requests to PCI Express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) bcma_core_pci_enable_crs(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &val16, sizeof(val16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) val16 |= (2 << 5); /* Max payload size of 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val16 |= (2 << 12); /* MRRS 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &val16, sizeof(val16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Enable PCI bridge BAR0 memory & master access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Enable PCI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Ok, ready to run, register it to the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * The following needs change, if we want to port hostmode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * to non-MIPS platform. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) io_map_base = (unsigned long)ioremap(pc_host->mem_resource.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) resource_size(&pc_host->mem_resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pc_host->pci_controller.io_map_base = io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) set_io_port_base(pc_host->pci_controller.io_map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Give some time to the PCI controller to configure itself with the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * values. Not waiting at this point causes crashes of the machine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) register_pci_controller(&pc_host->pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Early PCI fixup for a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* This is not a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (PCI_SLOT(dev->devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Enable PCI bridge bus mastering and memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (pcibios_enable_device(dev, ~0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pr_err("PCI: BCMA bridge enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Enable PCI bridge BAR1 prefetch and burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Early PCI fixup for all PCI-cores to set the correct memory address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int pos, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* This is not a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (PCI_SLOT(dev->devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (pos = 0; pos < 6; pos++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) res = &dev->resource[pos];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = pci_assign_resource(dev, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pr_err("PCI: Problem fixing up the addresses on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* This function is called when doing a pci_enable_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * We must first check if the device is a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct bcma_drv_pci_host *pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int readrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* This is not a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pr_info("PCI: Fixing up device %s\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Fix up interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev->irq = bcma_core_irq(pc_host->pdev->core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) readrq = pcie_get_readrq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (readrq > 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pr_info("change PCIe max read request size from %i to 128\n", readrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pcie_set_readrq(dev, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* PCI device IRQ mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct bcma_drv_pci_host *pc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* This is not a device on the PCI-core bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return bcma_core_irq(pc_host->pdev->core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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