^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom MIPS32 74K core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_BCM47XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bcm47xx_nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum bcma_boot_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) BCMA_BOOT_DEV_UNK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) BCMA_BOOT_DEV_ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) BCMA_BOOT_DEV_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) BCMA_BOOT_DEV_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) BCMA_BOOT_DEV_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The 47162a0 hangs when reading MIPS DMP registers registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* The 5357b0 hangs when reading USB20H DMP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dev->bus->chipinfo.pkg == 11 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev->id.id == BCMA_CORE_USB20_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline u32 mips_read32(struct bcma_drv_mips *mcore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return bcma_read32(mcore->core, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline void mips_write32(struct bcma_drv_mips *mcore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bcma_write32(mcore->core, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (bcma_core_mips_bcm47162a0_quirk(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return dev->core_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (bcma_core_mips_bcm5357b0_quirk(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return dev->core_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return flag & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Get the MIPS IRQ assignment for a specified device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * If unassigned, 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * If disabled, 5 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * If not supported, 6 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int bcma_core_mips_irq(struct bcma_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct bcma_device *mdev = dev->bus->drv_mips.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 irqflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) irqflag = bcma_core_mips_irqflag(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (irqflag == 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (irq = 0; irq <= 4; irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (1 << irqflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int oldirq = bcma_core_mips_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct bcma_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct bcma_device *mdev = bus->drv_mips.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 irqflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irqflag = bcma_core_mips_irqflag(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BUG_ON(oldirq == 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev->irq = irq + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* clear the old irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (oldirq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ~(1 << irqflag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else if (oldirq != 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* assign the new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (1 << irqflag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 irqinitmask = bcma_read32(mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) BCMA_MIPS_MIPS74K_INTMASK(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (irqinitmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* backplane irq line is in use, find out who uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * it and set user to irq 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) list_for_each_entry(core, &bus->cores, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if ((1 << bcma_core_mips_irqflag(core)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irqinitmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bcma_core_mips_set_irq(core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 1 << irqflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 coreid, u8 unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) core = bcma_find_core_unit(bus, coreid, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!core) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bcma_warn(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) coreid, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bcma_core_mips_set_irq(core, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char interrupts[25];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) char *ints = interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < ARRAY_SIZE(irq_name); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ints += sprintf(ints, " %s%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) irq_name[i], i == irq ? '*' : ' ');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bcma_debug(dev->bus, "core 0x%04x, irq:%s\n", dev->id.id, interrupts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) list_for_each_entry(core, &bus->cores, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct bcma_bus *bus = mcore->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return bcma_pmu_get_cpu_clock(&bus->drv_cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EXPORT_SYMBOL(bcma_cpu_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct bcma_drv_cc *cc = &bus->drv_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 cc_rev = cc->core->id.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (cc_rev == 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (core) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (bcma_aread32(core, BCMA_IOST) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return BCMA_BOOT_DEV_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return BCMA_BOOT_DEV_NAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return BCMA_BOOT_DEV_ROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (cc_rev == 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return BCMA_BOOT_DEV_NAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (cc->status & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return BCMA_BOOT_DEV_ROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BCMA_CC_FLASHT_PARA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return BCMA_BOOT_DEV_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return BCMA_BOOT_DEV_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return BCMA_BOOT_DEV_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct bcma_bus *bus = mcore->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) enum bcma_boot_dev boot_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Determine flash type this SoC boots from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) boot_dev = bcma_boot_dev(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (boot_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case BCMA_BOOT_DEV_PARALLEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case BCMA_BOOT_DEV_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_BCM47XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) BCMA_SOC_FLASH2_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case BCMA_BOOT_DEV_NAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #ifdef CONFIG_BCM47XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) BCMA_SOC_FLASH1_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct bcma_bus *bus = mcore->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (mcore->early_setup_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bcma_chipco_serial_init(&bus->drv_cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bcma_core_mips_nvram_init(mcore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mcore->early_setup_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct bcma_device *cpu, *pcie, *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * (IRQ flags > 7 are ignored when setting the interrupt masks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) i2s = bcma_find_core(bus, BCMA_CORE_I2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (cpu && pcie && i2s &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bcma_debug(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "Moved i2s interrupt to oob line 7 instead of 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void bcma_core_mips_init(struct bcma_drv_mips *mcore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct bcma_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bus = mcore->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (mcore->setup_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bcma_debug(bus, "Initializing MIPS core...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bcma_core_mips_early_init(mcore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bcma_fix_i2s_irqflag(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case BCMA_CHIP_ID_BCM4716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case BCMA_CHIP_ID_BCM4748:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case BCMA_CHIP_ID_BCM5356:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case BCMA_CHIP_ID_BCM47162:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case BCMA_CHIP_ID_BCM53572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case BCMA_CHIP_ID_BCM4749:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case BCMA_CHIP_ID_BCM4706:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) list_for_each_entry(core, &bus->cores, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) core->irq = bcma_core_irq(core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bcma_err(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "Unknown device (0x%x) found, can not configure IRQs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bus->chipinfo.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bcma_debug(bus, "IRQ reconfiguration done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bcma_core_mips_dump_irq(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mcore->setup_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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