Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define BCMA_GPIO_MAX_PINS	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	return !!bcma_chipco_gpio_in(cc, 1 << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 				int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				      int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	bcma_chipco_gpio_control(cc, 1 << gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* clear pulldown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Set pullup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* clear pullup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void bcma_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void bcma_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static struct irq_chip bcma_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.name		= "BCMA-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.irq_mask	= bcma_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.irq_unmask	= bcma_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct bcma_drv_cc *cc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct gpio_chip *gc = &cc->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long irqs = (val ^ pol) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (!irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	for_each_set_bit(gpio, &irqs, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct gpio_chip *chip = &cc->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct gpio_irq_chip *girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int hwirq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	hwirq = bcma_core_irq(cc->core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			  cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	bcma_chipco_gpio_intmask(cc, ~0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	girq->chip = &bcma_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	free_irq(bcma_core_irq(cc->core, 0), cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int bcma_gpio_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct gpio_chip *chip = &cc->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	chip->label		= "bcma_gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	chip->owner		= THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	chip->request		= bcma_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	chip->free		= bcma_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	chip->get		= bcma_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	chip->set		= bcma_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	chip->direction_input	= bcma_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	chip->direction_output	= bcma_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	chip->owner		= THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	chip->parent		= bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #if IS_BUILTIN(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	chip->of_node		= cc->core->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case BCMA_CHIP_ID_BCM4707:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case BCMA_CHIP_ID_BCM53572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case BCMA_CHIP_ID_BCM53573:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case BCMA_CHIP_ID_BCM47094:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		chip->ngpio	= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		chip->ngpio	= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * Register SoC GPIO devices with absolute GPIO pin base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * On MIPS, we don't have Device Tree and we can't use relative (per chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * GPIO numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * On some ARM devices, user space may want to access some system GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * pins directly, which is easier to do with a predictable GPIO base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (IS_BUILTIN(CONFIG_BCM47XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	    cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		chip->base		= bus->num * BCMA_GPIO_MAX_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		chip->base		= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	err = bcma_gpio_irq_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	err = gpiochip_add_data(chip, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		bcma_gpio_irq_exit(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int bcma_gpio_unregister(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bcma_gpio_irq_exit(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	gpiochip_remove(&cc->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }