^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ChipCommon Power Management Unit driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2007, 2011, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 offset, u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 ilp_ctl, alp_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) alp_hz = ilp_ctl * 32768 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (alp_hz + 50000) / 100000 * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 freq_tgt_target = 0, freq_tgt_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 pll0, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case BCMA_CHIP_ID_BCM43142:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* pmu2_xtaltab0_adfll_485 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (xtalfreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) freq_tgt_target = 0x50D52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) freq_tgt_target = 0x307FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 26000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) freq_tgt_target = 0x254EA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 37400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) freq_tgt_target = 0x19EF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 52000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) freq_tgt_target = 0x12A75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!freq_tgt_target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) xtalfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (freq_tgt_current == freq_tgt_target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bcma_debug(bus, "Target TGT frequency already set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Turn off PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case BCMA_CHIP_ID_BCM43142:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) BCMA_RES_4314_MACPHY_CLK_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bcma_wait_value(cc->core, BCMA_CLKCTLST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BCMA_CLKCTLST_HAVEHT, 0, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (cc->pmu.rev >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* TODO: Do we need to update OTP? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 xtalfreq = bcma_pmu_xtalfreq(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case BCMA_CHIP_ID_BCM43142:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (xtalfreq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) xtalfreq = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bcma_pmu2_pll_init0(cc, xtalfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 min_msk = 0, max_msk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case BCMA_CHIP_ID_BCM4313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) min_msk = 0x200D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) max_msk = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case BCMA_CHIP_ID_BCM43142:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) min_msk = BCMA_RES_4314_LPLDO_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BCMA_RES_4314_PMU_SLEEP_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BCMA_RES_4314_PMU_BG_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BCMA_RES_4314_CBUCK_LPOM_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) BCMA_RES_4314_CBUCK_PFM_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) BCMA_RES_4314_CLDO_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) BCMA_RES_4314_LPLDO2_LVM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) BCMA_RES_4314_WL_PMU_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BCMA_RES_4314_LDO3P3_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BCMA_RES_4314_OTP_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BCMA_RES_4314_WL_PWRSW_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BCMA_RES_4314_LQ_AVAIL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BCMA_RES_4314_LOGIC_RET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) BCMA_RES_4314_MEM_SLEEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BCMA_RES_4314_MACPHY_RET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) BCMA_RES_4314_WL_CORE_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) max_msk = 0x3FFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bus->chipinfo.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Set the resource masks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (min_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (max_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Add some delay; allow resources to come up and settle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Delay is required for SoC (early init).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) usleep_range(2000, 2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val |= BCMA_CHIPCTL_4331_EXTPA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else if (bus->chipinfo.rev > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case BCMA_CHIP_ID_BCM4313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * enable 12 mA drive strenth for 4313 and set chipControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * register bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bcma_chipco_chipctl_maskset(cc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) BCMA_CCTRL_4313_12MA_LED_DRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case BCMA_CHIP_ID_BCM4331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case BCMA_CHIP_ID_BCM43431:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Ext PA lines must be enabled for tx on BCM4331 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case BCMA_CHIP_ID_BCM43224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case BCMA_CHIP_ID_BCM43421:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * enable 12 mA drive strenth for 43224 and set chipControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * register bit 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (bus->chipinfo.rev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ~BCMA_CCTRL_43224_GPIO_TOGGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) BCMA_CCTRL_43224_GPIO_TOGGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bcma_chipco_chipctl_maskset(cc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bcma_chipco_chipctl_maskset(cc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bus->chipinfo.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void bcma_pmu_early_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 pmucap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (cc->core->id.rev >= 35 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!cc->pmu.core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bcma_warn(bus, "Couldn't find expected PMU core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!cc->pmu.core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cc->pmu.core = cc->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pmucap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void bcma_pmu_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (cc->pmu.rev == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ~BCMA_CC_PMU_CTL_NOILPONW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) BCMA_CC_PMU_CTL_NOILPONW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bcma_pmu_pll_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bcma_pmu_resources_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bcma_pmu_workarounds(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case BCMA_CHIP_ID_BCM4313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case BCMA_CHIP_ID_BCM43224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case BCMA_CHIP_ID_BCM43225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case BCMA_CHIP_ID_BCM43227:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case BCMA_CHIP_ID_BCM43228:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case BCMA_CHIP_ID_BCM4331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case BCMA_CHIP_ID_BCM43421:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case BCMA_CHIP_ID_BCM43428:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case BCMA_CHIP_ID_BCM43431:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case BCMA_CHIP_ID_BCM4716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case BCMA_CHIP_ID_BCM47162:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case BCMA_CHIP_ID_BCM4748:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case BCMA_CHIP_ID_BCM4749:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case BCMA_CHIP_ID_BCM53572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case BCMA_CHIP_ID_BCM6362:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* always 20Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 20000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case BCMA_CHIP_ID_BCM4706:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case BCMA_CHIP_ID_BCM5356:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* always 25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 25000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case BCMA_CHIP_ID_BCM43460:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case BCMA_CHIP_ID_BCM4352:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case BCMA_CHIP_ID_BCM4360:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 40000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 20000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return BCMA_CC_PMU_ALP_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Find the output of the "m" pll divider given pll controls that start with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 tmp, div, ndiv, p1, p2, fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) BUG_ON(!m || m > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Detect failure in clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (tmp & 0x40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 133 * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) BCMA_CC_PPL_MDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Do calculation in Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fc = bcma_pmu_get_alp_clock(cc) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fc = (p1 * ndiv * fc) / p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Return clock in Hertz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return (fc / div) * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 tmp, ndiv, p1div, p2div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BUG_ON(!m || m > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Get N, P1 and P2 dividers to determine CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clock = (25000000 / 4) * ndiv * p2div / p1div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Fixed reference clock 25MHz and m = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clock = (25000000 / 2) * ndiv * p2div / p1div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (m == BCMA_CC_PMU5_MAINPLL_SSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clock = clock / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* query bus clock frequency for PMU-enabled chipcommon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case BCMA_CHIP_ID_BCM4716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case BCMA_CHIP_ID_BCM4748:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case BCMA_CHIP_ID_BCM47162:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BCMA_CC_PMU5_MAINPLL_SSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case BCMA_CHIP_ID_BCM5356:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) BCMA_CC_PMU5_MAINPLL_SSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case BCMA_CHIP_ID_BCM4749:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BCMA_CC_PMU5_MAINPLL_SSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case BCMA_CHIP_ID_BCM4706:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return bcma_pmu_pll_clock_bcm4706(cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BCMA_CC_PMU4706_MAINPLL_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BCMA_CC_PMU5_MAINPLL_SSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case BCMA_CHIP_ID_BCM53572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 75000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return BCMA_CC_PMU_HT_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* query cpu clock frequency for PMU-enabled chipcommon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 300000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* New PMUs can have different clock for bus and CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (cc->pmu.rev >= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case BCMA_CHIP_ID_BCM4706:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return bcma_pmu_pll_clock_bcm4706(cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BCMA_CC_PMU4706_MAINPLL_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) BCMA_CC_PMU5_MAINPLL_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case BCMA_CHIP_ID_BCM5356:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case BCMA_CHIP_ID_BCM4749:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* On old PMUs CPU has the same clock as the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return bcma_pmu_get_bus_clock(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 phypll_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch (bus->chipinfo.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case BCMA_CHIP_ID_BCM5357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case BCMA_CHIP_ID_BCM4749:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case BCMA_CHIP_ID_BCM53572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* 5357[ab]0, 43236[ab]0, and 6362b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * BCM5357 needs to touch PLL1_PLLCTL[02],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * so offset PLL0_PLLCTL[02] by 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* RMW only the P1 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* RMW only the int feedback divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tmp = BCMA_CC_PMU_CTL_PLL_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case BCMA_CHIP_ID_BCM4331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case BCMA_CHIP_ID_BCM43431:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (spuravoid == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x11500014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x0FC00a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else if (spuravoid == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x11500014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x0F600a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x11100014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x03000a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tmp = BCMA_CC_PMU_CTL_PLL_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case BCMA_CHIP_ID_BCM43224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case BCMA_CHIP_ID_BCM43225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case BCMA_CHIP_ID_BCM43421:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (spuravoid == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x11500010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x000C0C06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x0F600a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x2001E920);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x11100010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0x000c0c06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x03000a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x200005c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) tmp = BCMA_CC_PMU_CTL_PLL_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case BCMA_CHIP_ID_BCM4716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case BCMA_CHIP_ID_BCM4748:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case BCMA_CHIP_ID_BCM47162:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (spuravoid == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x11500060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x080C0C06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x0F600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x2001E924);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x11100060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0x080c0c06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x03000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x200005c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case BCMA_CHIP_ID_BCM43131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case BCMA_CHIP_ID_BCM43217:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case BCMA_CHIP_ID_BCM43227:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case BCMA_CHIP_ID_BCM43228:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case BCMA_CHIP_ID_BCM43428:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* LCNXN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * PLL Settings for spur avoidance on/off mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * no on2 support for 43228A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (spuravoid == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x01100014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0x040C0C06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0x03140A08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x00333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x202C2820);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x11100014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x040c0c06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x03000a08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0x200005c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x88888815);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tmp = BCMA_CC_PMU_CTL_PLL_UPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bus->chipinfo.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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