^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ChipCommon B Unit driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 value, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned long deadline = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) val = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if ((val & mask) == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) } while (!time_after_eq(jiffies, deadline));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bcma_err(bus, "Timeout waiting for register %p\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct bcma_bus *bus = ccb->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *mii = ccb->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (ccb->setup_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ccb->setup_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ccb->mii = ioremap(ccb->core->addr_s[1], BCMA_CORE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (!ccb->mii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ccb->mii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iounmap(ccb->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }