^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom specific AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ChipCommon core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "bcma_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bcm47xx_wdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) value &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) value |= bcma_cc_read32(cc, offset) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bcma_cc_write32(cc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (cc->capabilities & BCMA_CC_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return bcma_pmu_get_alp_clock(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static bool bcma_core_cc_has_pmu_watchdog(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (cc->capabilities & BCMA_CC_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) WARN(bus->chipinfo.rev <= 1, "No watchdog available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 53573B0 and 53573B1 have bugged PMU watchdog. It can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * be enabled but timer can't be bumped. Use CC one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (bcma_core_cc_has_pmu_watchdog(cc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) nb = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) else if (cc->core->id.rev < 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) nb = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) nb = (cc->core->id.rev >= 37) ? 32 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) nb = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (nb == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return (1 << nb) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return bcma_chipco_watchdog_timer_set(cc, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ticks / cc->ticks_per_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (cc->capabilities & BCMA_CC_CAP_PMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return bcma_chipco_get_alp_clock(cc) / 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* based on 32KHz ILP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return bcma_chipco_get_alp_clock(cc) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct bcm47xx_wdt wdt = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bus->chipinfo.rev <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_debug("No watchdog on 53573A0 / 53573A1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) wdt.driver_data = cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) wdt.max_timer_ms =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bus->num, &wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) sizeof(wdt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cc->watchdog = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case BCMA_CC_FLASHT_STSER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case BCMA_CC_FLASHT_ATSER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bcma_debug(bus, "Found serial flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bcma_sflash_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case BCMA_CC_FLASHT_PARA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bcma_debug(bus, "Found parallel flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bcma_pflash_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bcma_err(bus, "Flash type not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cc->core->id.rev == 38 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bcma_debug(bus, "Found NAND flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bcma_nflash_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (cc->early_setup_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spin_lock_init(&cc->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (cc->core->id.rev >= 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (cc->core->id.rev >= 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (cc->capabilities & BCMA_CC_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bcma_pmu_early_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (bus->hosttype == BCMA_HOSTTYPE_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bcma_core_chipcommon_flash_detect(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cc->early_setup_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 leddc_on = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 leddc_off = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (cc->setup_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bcma_core_chipcommon_early_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (cc->core->id.rev >= 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 pullup = 0, pulldown = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pullup = 0x402e0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pulldown = 0x20500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (cc->capabilities & BCMA_CC_CAP_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bcma_pmu_init(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (cc->capabilities & BCMA_CC_CAP_PCTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bcma_err(cc->core->bus, "Power control not implemented!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (cc->core->id.rev >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (cc->core->bus->sprom.leddc_on_time &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cc->core->bus->sprom.leddc_off_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) leddc_on = cc->core->bus->sprom.leddc_on_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) leddc_off = cc->core->bus->sprom.leddc_off_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cc->setup_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) maxt = bcma_chipco_watchdog_get_max_timer(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (bcma_core_cc_has_pmu_watchdog(cc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ticks == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else if (ticks > maxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ticks = maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct bcma_bus *bus = cc->core->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bcma_core_set_clockmode(cc->core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ticks > maxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ticks = maxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* instant NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * If the bit is set to 0, chipcommon controlls this GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * if the bit is set to 1, it is used by some part of the chip and not our code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (cc->core->id.rev < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (cc->core->id.rev < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spin_lock_irqsave(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_unlock_irqrestore(&cc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_BCMA_DRIVER_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int ccrev = cc->core->id.rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct bcma_serial_port *ports = cc->serial_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ccrev >= 11 && ccrev != 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) baud_base = bcma_chipco_get_alp_clock(cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ccrev >= 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Turn off UART clock before switching clocksource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bcma_cc_write32(cc, BCMA_CC_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) bcma_cc_read32(cc, BCMA_CC_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) & ~BCMA_CC_CORECTL_UARTCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Set the override bit so we don't divide it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bcma_cc_write32(cc, BCMA_CC_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bcma_cc_read32(cc, BCMA_CC_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) | BCMA_CC_CORECTL_UARTCLK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ccrev >= 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Re-enable the UART clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bcma_cc_write32(cc, BCMA_CC_CORECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) bcma_cc_read32(cc, BCMA_CC_CORECTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) | BCMA_CC_CORECTL_UARTCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ccrev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) irq = bcma_core_irq(cc->core, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Determine the registers of the UARTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < cc->nr_serial_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) (i * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ports[i].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ports[i].baud_base = baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ports[i].reg_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #endif /* CONFIG_BCMA_DRIVER_MIPS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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