^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Register map access API - SPI AVMM support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This driver implements the regmap operations for a generic SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * master to access the registers of the spi slave chip which has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Avalone bus in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * in the spi slave chip. The IP acts as a bridge to convert encoded streams of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * bytes from the host to the internal register read/write on Avalon bus. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * order to issue register access requests to the slave chip, the host should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * send formatted bytes that conform to the transfer protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The transfer protocol contains 3 layers: transaction layer, packet layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * and physical layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Reference Documents could be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * introduction to the protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Chapter "Avalon Packets to Transactions Converter Core" describes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * the transaction layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Chapter "Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * describes the packet layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Chapter "Avalon-ST Serial Peripheral Interface Core" describes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * physical layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * When host issues a regmap read/write, the driver will transform the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * to byte stream layer by layer. It formats the register addr, value and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * length to the transaction layer request, then converts the request to packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * layer bytes stream and then to physical layer bytes stream. Finally the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * driver sends the formatted byte stream over SPI bus to the slave chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * The spi-avmm IP on the slave chip decodes the byte stream and initiates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * register read/write on its internal Avalon bus, and then encodes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * response to byte stream and sends back to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The driver receives the byte stream, reverses the 3 layers transformation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * and finally gets the response value (read out data for register read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * successful written size for register write).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PKT_SOP 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PKT_EOP 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PKT_CHANNEL 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PKT_ESC 0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_IDLE 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PHY_ESC 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TRANS_CODE_WRITE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TRANS_CODE_SEQ_WRITE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TRANS_CODE_READ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TRANS_CODE_SEQ_READ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TRANS_CODE_NO_TRANS 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPI_AVMM_XFER_TIMEOUT (msecs_to_jiffies(200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* slave's register addr is 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPI_AVMM_REG_SIZE 4UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* slave's register value is 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPI_AVMM_VAL_SIZE 4UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * max rx size could be larger. But considering the buffer consuming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * it is proper that we limit 1KB xfer at max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX_READ_CNT 256UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX_WRITE_CNT 1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct trans_req_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __be16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __be32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct trans_resp_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 r_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __be16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TRANS_REQ_HD_SIZE (sizeof(struct trans_req_header))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TRANS_RESP_HD_SIZE (sizeof(struct trans_resp_header))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * In transaction layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * the write request format is: Transaction request header + data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * the read request format is: Transaction request header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * the write response format is: Transaction response header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * the read response format is: pure data, no Transaction response header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TRANS_WR_TX_SIZE(n) (TRANS_REQ_HD_SIZE + SPI_AVMM_VAL_SIZE * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TRANS_RD_TX_SIZE TRANS_REQ_HD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TRANS_TX_MAX TRANS_WR_TX_SIZE(MAX_WRITE_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TRANS_RD_RX_SIZE(n) (SPI_AVMM_VAL_SIZE * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TRANS_WR_RX_SIZE TRANS_RESP_HD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TRANS_RX_MAX TRANS_RD_RX_SIZE(MAX_READ_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* tx & rx share one transaction layer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TRANS_BUF_SIZE ((TRANS_TX_MAX > TRANS_RX_MAX) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TRANS_TX_MAX : TRANS_RX_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * In tx phase, the host prepares all the phy layer bytes of a request in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * phy buffer and sends them in a batch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The packet layer and physical layer defines several special chars for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * various purpose, when a transaction layer byte hits one of these special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * chars, it should be escaped. The escape rule is, "Escape char first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * following the byte XOR'ed with 0x20".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * This macro defines the max possible length of the phy data. In the worst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * case, all transaction layer bytes need to be escaped (so the data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * doubles), plus 4 special chars (SOP, CHANNEL, CHANNEL_NUM, EOP). Finally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * we should make sure the length is aligned to SPI BPW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PHY_TX_MAX ALIGN(2 * TRANS_TX_MAX + 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * length of the rx bit stream is unpredictable. So the driver reads the words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * one by one, and parses each word immediately into transaction layer buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Only one word length of phy buffer is used for rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_BUF_SIZE PHY_TX_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * struct spi_avmm_bridge - SPI slave to AVMM bus master bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @spi: spi slave associated with this bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @word_len: bytes of word for spi transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @trans_len: length of valid data in trans_buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @phy_len: length of valid data in phy_buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @trans_buf: the bridge buffer for transaction layer data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @phy_buf: the bridge buffer for physical layer data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @swap_words: the word swapping cb for phy data. NULL if not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * As a device's registers are implemented on the AVMM bus address space, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * requires the driver to issue formatted requests to spi slave to AVMM bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * master bridge to perform register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct spi_avmm_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned char word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int phy_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* bridge buffer used in translation between protocol layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) char trans_buf[TRANS_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) char phy_buf[PHY_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void (*swap_words)(char *buf, unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void br_swap_words_32(char *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 *p = (u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) count = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *p = swab32p(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Format transaction layer data in br->trans_buf according to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * access request, Store valid transaction layer data length in br->trans_len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int br_trans_tx_prepare(struct spi_avmm_bridge *br, bool is_read, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 *wr_val, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct trans_req_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le32 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (is_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) code = TRANS_CODE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) code = TRANS_CODE_SEQ_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) code = TRANS_CODE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) code = TRANS_CODE_SEQ_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) header = (struct trans_req_header *)br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) header->code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) header->rsvd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) header->size = cpu_to_be16((u16)count * SPI_AVMM_VAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) header->addr = cpu_to_be32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) trans_len = TRANS_REQ_HD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!is_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) trans_len += SPI_AVMM_VAL_SIZE * count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (trans_len > sizeof(br->trans_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) data = (__le32 *)(br->trans_buf + TRANS_REQ_HD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *data++ = cpu_to_le32(*wr_val++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Store valid trans data length for next layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) br->trans_len = trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Convert transaction layer data (in br->trans_buf) to phy layer data, store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * them in br->phy_buf. Pad the phy_buf aligned with SPI's BPW. Store valid phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * layer data length in br->phy_len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * with PHY_IDLE, then the slave will just drop them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * The driver will not simply pad 4a at the tail. The concern is that driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * will not store MISO data during tx phase, if the driver pads 4a at the tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * it is possible that if the slave is fast enough to response at the padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * time. As a result these rx bytes are lost. In the following case, 7a,7c,00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * will lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * MOSI ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|4a|4a|4a| |XX|XX|...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * MISO ...|4a|4a|4a|4a| |4a|4a|4a|4a| |4a|4a|4a|4a| |4a|7a|7c|00| |78|56|...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * So the driver moves EOP and bytes after EOP to the end of the aligned size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * then fill the hole with PHY_IDLE. As following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * before pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * after pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|4a| |4a|4a|7b|40|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Then if the slave will not get the entire packet before the tx phase is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * over, it can't responsed to anything either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int br_pkt_phy_tx_prepare(struct spi_avmm_bridge *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) char *tb, *tb_end, *pb, *pb_limit, *pb_eop = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int aligned_phy_len, move_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool need_esc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tb = br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tb_end = tb + br->trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pb = br->phy_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pb_limit = pb + ARRAY_SIZE(br->phy_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *pb++ = PKT_SOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * The driver doesn't support multiple channels so the channel number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * is always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *pb++ = PKT_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *pb++ = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for (; pb < pb_limit && tb < tb_end; pb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (need_esc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *pb = *tb++ ^ 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) need_esc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* EOP should be inserted before the last valid char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (tb == tb_end - 1 && !pb_eop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *pb = PKT_EOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pb_eop = pb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * insert an ESCAPE char if the data value equals any special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * char.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (*tb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case PKT_SOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case PKT_EOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case PKT_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case PKT_ESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *pb = PKT_ESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) need_esc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case PHY_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case PHY_ESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *pb = PHY_ESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) need_esc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *pb = *tb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* The phy buffer is used out but transaction layer data remains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (tb < tb_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Store valid phy data length for spi transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) br->phy_len = pb - br->phy_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (br->word_len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Do phy buf padding if word_len > 1 byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) aligned_phy_len = ALIGN(br->phy_len, br->word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (aligned_phy_len > sizeof(br->phy_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (aligned_phy_len == br->phy_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* move EOP and bytes after EOP to the end of aligned size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) move_size = pb - pb_eop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) memmove(&br->phy_buf[aligned_phy_len - move_size], pb_eop, move_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* fill the hole with PHY_IDLEs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) memset(pb_eop, PHY_IDLE, aligned_phy_len - br->phy_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* update the phy data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) br->phy_len = aligned_phy_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * In tx phase, the slave only returns PHY_IDLE (0x4a). So the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * ignore rx in tx phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int br_do_tx(struct spi_avmm_bridge *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* reorder words for spi transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (br->swap_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) br->swap_words(br->phy_buf, br->phy_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* send all data in phy_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return spi_write(br->spi, br->phy_buf, br->phy_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * This function read the rx byte stream from SPI word by word and convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * them to transaction layer data in br->trans_buf. It also stores the length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * of rx transaction layer data in br->trans_len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The slave may send an unknown number of PHY_IDLEs in rx phase, so we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * prepare a fixed length buffer to receive all of the rx data in a batch. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * have to read word by word and convert them to transaction layer data at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bool eop_found = false, channel_found = false, esc_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bool valid_word = false, last_try = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct device *dev = &br->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) char *pb, *tb_limit, *tb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned long poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tb_limit = br->trans_buf + ARRAY_SIZE(br->trans_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pb = br->phy_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) while (tb < tb_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = spi_read(br->spi, pb, br->word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* reorder the word back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (br->swap_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) br->swap_words(pb, br->word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) valid_word = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < br->word_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* drop everything before first SOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!tb && pb[i] != PKT_SOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* drop PHY_IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (pb[i] == PHY_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) valid_word = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * We don't support multiple channels, so error out if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * a non-zero channel number is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (channel_found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (pb[i] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(dev, "%s channel num != 0\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) channel_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) switch (pb[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case PKT_SOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * reset the parsing if a second SOP appears.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tb = br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) eop_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) channel_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) esc_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case PKT_EOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * No special char is expected after ESC char.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * No special char (except ESC & PHY_IDLE) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * expected after EOP char.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * The special chars are all dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (esc_found || eop_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) eop_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case PKT_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (esc_found || eop_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) channel_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PKT_ESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PHY_ESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (esc_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) esc_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Record the normal byte in trans_buf. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (esc_found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *tb++ = pb[i] ^ 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) esc_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *tb++ = pb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * We get the last normal byte after EOP, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * time we finish. Normally the function should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * return here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (eop_found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) br->trans_len = tb - br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (valid_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* update poll timeout when we get valid word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) last_try = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * We timeout when rx keeps invalid for some time. But
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * it is possible we are scheduled out for long time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * after a spi_read. So when we are scheduled in, a SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * timeout happens. But actually HW may have worked fine and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * has been ready long time ago. So we need to do an extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * read, if we get a valid word then we could continue rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * otherwise real a HW issue happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (last_try)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (time_after(jiffies, poll_timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) last_try = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * We have used out all transfer layer buffer but cannot find the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * of the byte stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(dev, "%s transfer buffer is full but rx doesn't end\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * For read transactions, the avmm bus will directly return register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * without transaction response header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int br_rd_trans_rx_parse(struct spi_avmm_bridge *br,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 *val, unsigned int expected_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int i, trans_len = br->trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le32 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (expected_count * SPI_AVMM_VAL_SIZE != trans_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) data = (__le32 *)br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i = 0; i < expected_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *val++ = le32_to_cpu(*data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * For write transactions, the slave will return a transaction response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int br_wr_trans_rx_parse(struct spi_avmm_bridge *br,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int expected_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int trans_len = br->trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct trans_resp_header *resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u16 val_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (trans_len != TRANS_RESP_HD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) resp = (struct trans_resp_header *)br->trans_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) code = resp->r_code ^ 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val_len = be16_to_cpu(resp->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!val_len || val_len != expected_count * SPI_AVMM_VAL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* error out if the trans code doesn't align with the val size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if ((val_len == SPI_AVMM_VAL_SIZE && code != TRANS_CODE_WRITE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) (val_len > SPI_AVMM_VAL_SIZE && code != TRANS_CODE_SEQ_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int do_reg_access(void *context, bool is_read, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int *value, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct spi_avmm_bridge *br = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* invalidate bridge buffers first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) br->trans_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) br->phy_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = br_trans_tx_prepare(br, is_read, reg, value, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = br_pkt_phy_tx_prepare(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = br_do_tx(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = br_do_rx_and_pkt_phy_parse(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return br_rd_trans_rx_parse(br, value, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return br_wr_trans_rx_parse(br, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int regmap_spi_avmm_gather_write(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const void *reg_buf, size_t reg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const void *val_buf, size_t val_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (reg_len != SPI_AVMM_REG_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return do_reg_access(context, false, *(u32 *)reg_buf, (u32 *)val_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val_len / SPI_AVMM_VAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int regmap_spi_avmm_write(void *context, const void *data, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (bytes < SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return regmap_spi_avmm_gather_write(context, data, SPI_AVMM_REG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) data + SPI_AVMM_REG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bytes - SPI_AVMM_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int regmap_spi_avmm_read(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) const void *reg_buf, size_t reg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) void *val_buf, size_t val_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (reg_len != SPI_AVMM_REG_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return do_reg_access(context, true, *(u32 *)reg_buf, val_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (val_len / SPI_AVMM_VAL_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct spi_avmm_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) spi_avmm_bridge_ctx_gen(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct spi_avmm_bridge *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Only support BPW == 8 or 32 now. Try 32 BPW first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spi->mode = SPI_MODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spi->bits_per_word = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (spi_setup(spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (spi_setup(spi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) br = kzalloc(sizeof(*br), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) br->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) br->word_len = spi->bits_per_word / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (br->word_len == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * The protocol requires little endian byte order but MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * first. So driver needs to swap the byte order word by word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * if word length > 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) br->swap_words = br_swap_words_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void spi_avmm_bridge_ctx_free(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) kfree(context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const struct regmap_bus regmap_spi_avmm_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .write = regmap_spi_avmm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .gather_write = regmap_spi_avmm_gather_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .read = regmap_spi_avmm_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .max_raw_read = SPI_AVMM_VAL_SIZE * MAX_READ_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .max_raw_write = SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .free_context = spi_avmm_bridge_ctx_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct regmap *__regmap_init_spi_avmm(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) const struct regmap_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct lock_class_key *lock_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) const char *lock_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct spi_avmm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) bridge = spi_avmm_bridge_ctx_gen(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (IS_ERR(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ERR_CAST(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) map = __regmap_init(&spi->dev, ®map_spi_avmm_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) bridge, config, lock_key, lock_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spi_avmm_bridge_ctx_free(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ERR_CAST(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) EXPORT_SYMBOL_GPL(__regmap_init_spi_avmm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct regmap *__devm_regmap_init_spi_avmm(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const struct regmap_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct lock_class_key *lock_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) const char *lock_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct spi_avmm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) bridge = spi_avmm_bridge_ctx_gen(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (IS_ERR(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ERR_CAST(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) map = __devm_regmap_init(&spi->dev, ®map_spi_avmm_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bridge, config, lock_key, lock_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spi_avmm_bridge_ctx_free(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ERR_CAST(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) EXPORT_SYMBOL_GPL(__devm_regmap_init_spi_avmm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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