^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Register map access API - SCCB support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * sccb_is_available - Check if the adapter supports SCCB protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * @adap: I2C adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Return true if the I2C adapter is capable of using SCCB helper functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static bool sccb_is_available(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 needed_funcs = I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * If we ever want support for hardware doing SCCB natively, we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * introduce a sccb_xfer() callback to struct i2c_algorithm and check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * for it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return (i2c_get_functionality(adap) & needed_funcs) == needed_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * regmap_sccb_read - Read data from SCCB slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @context: Device that will be interacted with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @reg: Register to be read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @val: Pointer to store read value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * This executes the 2-phase write transmission cycle that is followed by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 2-phase read transmission cycle, returning negative errno else zero on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int regmap_sccb_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) i2c_lock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ret = __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) I2C_SMBUS_WRITE, reg, I2C_SMBUS_BYTE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) I2C_SMBUS_READ, 0, I2C_SMBUS_BYTE, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *val = data.byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) i2c_unlock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * regmap_sccb_write - Write data to SCCB slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @context: Device that will be interacted with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @reg: Register to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @val: Value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * This executes the SCCB 3-phase write transmission cycle, returning negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * errno else zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int regmap_sccb_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return i2c_smbus_write_byte_data(i2c, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct regmap_bus regmap_sccb_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reg_write = regmap_sccb_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg_read = regmap_sccb_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct regmap_bus *regmap_get_sccb_bus(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (config->val_bits == 8 && config->reg_bits == 8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sccb_is_available(i2c->adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ®map_sccb_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct regmap *__regmap_init_sccb(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct regmap_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct lock_class_key *lock_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *lock_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct regmap_bus *bus = regmap_get_sccb_bus(i2c, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (IS_ERR(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ERR_CAST(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return __regmap_init(&i2c->dev, bus, &i2c->dev, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) lock_key, lock_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXPORT_SYMBOL_GPL(__regmap_init_sccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regmap *__devm_regmap_init_sccb(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct regmap_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct lock_class_key *lock_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const char *lock_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct regmap_bus *bus = regmap_get_sccb_bus(i2c, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (IS_ERR(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ERR_CAST(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return __devm_regmap_init(&i2c->dev, bus, &i2c->dev, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) lock_key, lock_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(__devm_regmap_init_sccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags