^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the on-board character LCD found on some ARM reference boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * https://en.wikipedia.org/wiki/HD44780_Character_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Currently it will just display the text "ARM Linux" and the linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Linus Walleij <triad@df.lth.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <generated/utsrelease.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRIVERNAME "arm-charlcd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CHARLCD_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Offsets to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CHAR_COM 0x00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CHAR_DAT 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CHAR_RD 0x08U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CHAR_RAW 0x0CU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CHAR_MASK 0x10U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CHAR_STAT 0x14U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CHAR_RAW_CLEAR 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CHAR_RAW_VALID 0x00000100U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Hitachi HD44780 display commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HD_CLEAR 0x01U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HD_HOME 0x02U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HD_ENTRYMODE 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HD_ENTRYMODE_INCREMENT 0x02U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HD_ENTRYMODE_SHIFT 0x01U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HD_DISPCTRL 0x08U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HD_DISPCTRL_ON 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HD_DISPCTRL_CURSOR_ON 0x02U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HD_DISPCTRL_CURSOR_BLINK 0x01U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HD_CRSR_SHIFT 0x10U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HD_CRSR_SHIFT_DISPLAY 0x08U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HD_CRSR_SHIFT_DISPLAY_RIGHT 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HD_FUNCSET 0x20U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HD_FUNCSET_8BIT 0x10U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HD_FUNCSET_2_LINES 0x08U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HD_FUNCSET_FONT_5X10 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HD_SET_CGRAM 0x40U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HD_SET_DDRAM 0x80U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HD_BUSY_FLAG 0x80U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct charlcd - Private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @dev: a pointer back to containing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @phybase: the offset to the controller in physical memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @physize: the size of the physical page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @virtbase: the offset to the controller in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @irq: reserved interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @complete: completion structure for the last LCD command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @init_work: delayed work structure to initialize the display on boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct charlcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 phybase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 physize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct delayed_work init_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static irqreturn_t charlcd_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct charlcd *lcd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) status = readl(lcd->virtbase + CHAR_STAT) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) complete(&lcd->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_info(lcd->dev, "Spurious IRQ (%02x)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void charlcd_wait_complete_irq(struct charlcd *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = wait_for_completion_interruptible_timeout(&lcd->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CHARLCD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Disable IRQ after completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(0x00, lcd->virtbase + CHAR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(lcd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "wait_for_completion_interruptible_timeout() "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "returned %d waiting for ready\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(lcd->dev, "charlcd controller timed out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "waiting for ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u8 charlcd_4bit_read_char(struct charlcd *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* If we can, use an IRQ to wait for the data, else poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (lcd->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) charlcd_wait_complete_irq(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (!(val & CHAR_RAW_VALID) && i < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val = readl(lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Read the 4 high bits of the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) data = readl(lcd->virtbase + CHAR_RD) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The second read for the low bits does not trigger an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * so in this case we have to poll for the 4 lower bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) while (!(val & CHAR_RAW_VALID) && i < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = readl(lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Read the 4 low bits of the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) data |= (readl(lcd->virtbase + CHAR_RD) >> 4) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static bool charlcd_4bit_read_bf(struct charlcd *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (lcd->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * If we'll use IRQs to wait for the busyflag, clear any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * pending flag and enable IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init_completion(&lcd->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(0x01, lcd->virtbase + CHAR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) readl(lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return charlcd_4bit_read_char(lcd) & HD_BUSY_FLAG ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void charlcd_4bit_wait_busy(struct charlcd *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int retries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) while (charlcd_4bit_read_bf(lcd) && retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(lcd->dev, "timeout waiting for busyflag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void charlcd_4bit_command(struct charlcd *lcd, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 cmdlo = (cmd << 4) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 cmdhi = (cmd & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(cmdhi, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(cmdlo, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) charlcd_4bit_wait_busy(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void charlcd_4bit_char(struct charlcd *lcd, u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 chlo = (ch << 4) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 chhi = (ch & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(chhi, lcd->virtbase + CHAR_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(chlo, lcd->virtbase + CHAR_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) charlcd_4bit_wait_busy(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void charlcd_4bit_print(struct charlcd *lcd, int line, const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * We support line 0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Line 1 runs from 0x00..0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Line 2 runs from 0x28..0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (line == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else if (line == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) offset = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Set offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) charlcd_4bit_command(lcd, HD_SET_DDRAM | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Send string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < strlen(str) && i < 0x28; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) charlcd_4bit_char(lcd, str[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void charlcd_4bit_init(struct charlcd *lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* These commands cannot be checked with the busy flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Go to 4bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel(HD_FUNCSET, lcd->virtbase + CHAR_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 4bit mode, 2 lines, 5x8 font, after this the number of lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * and the font cannot be changed until the next initialization sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) charlcd_4bit_command(lcd, HD_FUNCSET | HD_FUNCSET_2_LINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) charlcd_4bit_command(lcd, HD_ENTRYMODE | HD_ENTRYMODE_INCREMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) charlcd_4bit_command(lcd, HD_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) charlcd_4bit_command(lcd, HD_HOME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Put something useful in the display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) charlcd_4bit_print(lcd, 0, "ARM Linux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) charlcd_4bit_print(lcd, 1, UTS_RELEASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void charlcd_init_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct charlcd *lcd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) container_of(work, struct charlcd, init_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) charlcd_4bit_init(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int __init charlcd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct charlcd *lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) lcd = kzalloc(sizeof(struct charlcd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!lcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) lcd->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) goto out_no_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) lcd->phybase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) lcd->physize = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (request_mem_region(lcd->phybase, lcd->physize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DRIVERNAME) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto out_no_memregion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) lcd->virtbase = ioremap(lcd->phybase, lcd->physize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!lcd->virtbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto out_no_memregion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) lcd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* If no IRQ is supplied, we'll survive without it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (lcd->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (request_irq(lcd->irq, charlcd_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DRIVERNAME, lcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto out_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) platform_set_drvdata(pdev, lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Initialize the display in a delayed work, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * it is VERY slow and would slow down the boot of the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) INIT_DELAYED_WORK(&lcd->init_work, charlcd_init_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) schedule_delayed_work(&lcd->init_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_info(&pdev->dev, "initialized ARM character LCD at %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) lcd->phybase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) out_no_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) iounmap(lcd->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) out_no_memregion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) release_mem_region(lcd->phybase, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) out_no_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) kfree(lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int charlcd_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct charlcd *lcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Power the display off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) charlcd_4bit_command(lcd, HD_DISPCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int charlcd_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct charlcd *lcd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Turn the display back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct dev_pm_ops charlcd_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .suspend = charlcd_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .resume = charlcd_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct of_device_id charlcd_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { .compatible = "arm,versatile-lcd", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct platform_driver charlcd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = DRIVERNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .pm = &charlcd_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .of_match_table = of_match_ptr(charlcd_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) builtin_platform_driver_probe(charlcd_driver, charlcd_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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