^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRIVER_ATM_ZATM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRIVER_ATM_ZATM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/atm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sonet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEV_LABEL "zatm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOW_MARK 12 /* start adding new buffers if less than 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HIGH_MARK 30 /* stop adding buffers after reaching 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OFF_CNG_THRES 5 /* threshold for offset changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RX_SIZE 2 /* RX lookup entry size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NR_POOLS 32 /* number of free buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define POOL_SIZE 8 /* buffer entry size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NR_SHAPERS 16 /* number of shapers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SHAPER_SIZE 4 /* shaper entry size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RING_ENTRIES 32 /* ring entries (without back pointer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RING_WORDS 4 /* ring element size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NR_MBX 4 /* four mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MBX_RX_0 0 /* mailbox indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MBX_RX_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MBX_TX_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MBX_TX_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct zatm_vcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*-------------------------------- RX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int rx_chan; /* RX channel, 0 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int pool; /* free buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*-------------------------------- TX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int tx_chan; /* TX channel, 0 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int shaper; /* shaper, <0 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sk_buff_head tx_queue; /* list of buffers in transit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) wait_queue_head_t tx_wait; /* for close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 *ring; /* transmit ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ring_curr; /* current write position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int txing; /* number of transmits in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sk_buff_head backlog; /* list of buffers waiting for ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct zatm_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*-------------------------------- TX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int tx_bw; /* remaining bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 free_shapers; /* bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ubr; /* UBR shaper; -1 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ubr_ref_cnt; /* number of VCs using UBR shaper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*-------------------------------- RX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int pool_ref[NR_POOLS]; /* free buffer pool usage counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) volatile struct sk_buff *last_free[NR_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* last entry in respective pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*-------------------------------- maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct atm_vcc **tx_map; /* TX VCCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct atm_vcc **rx_map; /* RX VCCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int chans; /* map size, must be 2^n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*-------------------------------- mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long mbx_start[NR_MBX];/* start addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dma_addr_t mbx_dma[NR_MBX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 mbx_end[NR_MBX]; /* end offset (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*-------------------------------- other pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 pool_base; /* Free buffer pool dsc (word addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*-------------------------------- ZATM links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct atm_dev *more; /* other ZATM devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*-------------------------------- general information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int mem; /* RAM on board (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int khz; /* timer clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int copper; /* PHY type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char irq; /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int base; /* IO base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_dev *pci_dev; /* PCI stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct zatm_skb_prv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct atm_skb_data _; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 *dsc; /* pointer to skb's descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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