^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Written 1995 by Werner Almesberger, EPFL LRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRIVERS_ATM_uPD98402_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRIVERS_ATM_uPD98402_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define uPD98402_CMR 0x00 /* Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define uPD98402_MDR 0x01 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define uPD98402_PIMR 0x03 /* PHY Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define uPD98402_ACR 0x04 /* Alarm Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define uPD98402_PCR 0x06 /* Performance Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define uPD98402_B1ECT 0x09 /* B1 Error Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define uPD98402_B2ECT 0x0a /* B2 Error Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define uPD98402_B3ECT 0x0b /* B3 Error Count Regster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define uPD98402_PFECB 0x0c /* Path FEBE Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define uPD98402_LECCT 0x0d /* Line FEBE Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define uPD98402_HECCT 0x0e /* HEC Error Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define uPD98402_FJCT 0x0f /* Frequence Justification Count Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define uPD98402_PCOMR 0x11 /* Perf. Counter Overflow Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define uPD98402_C11T 0x20 /* C11T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define uPD98402_C12T 0x21 /* C12T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define uPD98402_C13T 0x22 /* C13T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define uPD98402_F1T 0x23 /* F1T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define uPD98402_K2T 0x25 /* K2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define uPD98402_C2T 0x26 /* C2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define uPD98402_F2T 0x27 /* F2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define uPD98402_C11R 0x30 /* C11T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define uPD98402_C12R 0x31 /* C12T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define uPD98402_C13R 0x32 /* C13T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define uPD98402_F1R 0x33 /* F1T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define uPD98402_K2R 0x35 /* K2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define uPD98402_C2R 0x36 /* C2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define uPD98402_F2R 0x37 /* F2T Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CMR is at 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define uPD98402_CMR_PFRF 0x01 /* Send path FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define uPD98402_CMR_LFRF 0x02 /* Send line FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define uPD98402_CMR_PAIS 0x04 /* Send path AIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define uPD98402_CMR_LAIS 0x08 /* Send line AIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* MDR is at 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define uPD98402_MDR_ALP 0x01 /* ATM layer loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define uPD98402_MDR_TPLP 0x02 /* PMD loopback, to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define uPD98402_MDR_RPLP 0x04 /* PMD loopback, to network */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define uPD98402_MDR_SS0 0x08 /* SS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define uPD98402_MDR_SS1 0x10 /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define uPD98402_MDR_SS_MASK 0x18 /* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define uPD98402_MDR_SS_SHIFT 3 /* shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define uPD98402_MDR_HEC 0x20 /* disable HEC inbound processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define uPD98402_MDR_FSR 0x40 /* disable frame scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define uPD98402_MDR_CSR 0x80 /* disable cell scrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PICR is at 0x02, PIMR is at 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define uPD98402_INT_PFM 0x01 /* performance counter has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define uPD98402_INT_ALM 0x02 /* line fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define uPD98402_INT_RFO 0x04 /* receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define uPD98402_INT_PCO 0x08 /* performance counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define uPD98402_INT_OTD 0x20 /* OTD has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define uPD98402_INT_LOS 0x40 /* Loss Of Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define uPD98402_INT_LOF 0x80 /* Loss Of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ACR is as 0x04, ACMR is at 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define uPD98402_ALM_PFRF 0x01 /* path FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define uPD98402_ALM_LFRF 0x02 /* line FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define uPD98402_ALM_PAIS 0x04 /* path AIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define uPD98402_ALM_LAIS 0x08 /* line AIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define uPD98402_ALM_LOD 0x10 /* loss of delineation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define uPD98402_ALM_LOP 0x20 /* loss of pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define uPD98402_ALM_OOF 0x40 /* out of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* PCR is at 0x06, PCMR is at 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define uPD98402_PFM_PFEB 0x01 /* path FEBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define uPD98402_PFM_LFEB 0x02 /* line FEBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define uPD98402_PFM_B3E 0x04 /* B3 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define uPD98402_PFM_B2E 0x08 /* B2 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define uPD98402_PFM_B1E 0x10 /* B1 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define uPD98402_PFM_FJ 0x20 /* frequency justification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* IACM is at 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define uPD98402_IACM_PFRF 0x01 /* don't generate path FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define uPD98402_IACM_LFRF 0x02 /* don't generate line FERF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PCOCR is at 0x010, PCOMR is at 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define uPD98402_PCO_B1EC 0x01 /* B1ECT overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define uPD98402_PCO_B2EC 0x02 /* B2ECT overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define uPD98402_PCO_B3EC 0x04 /* B3ECT overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define uPD98402_PCO_PFBC 0x08 /* PFEBC overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define uPD98402_PCO_LFBC 0x10 /* LFEVC overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define uPD98402_PCO_HECC 0x20 /* HECCT overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define uPD98402_PCO_FJC 0x40 /* FJCT overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int uPD98402_init(struct atm_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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