Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /* Written 1995 by Werner Almesberger, EPFL LRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef DRIVERS_ATM_uPD98401_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define DRIVERS_ATM_uPD98401_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MAX_CRAM_SIZE	(1 << 18)	/* 2^18 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define RAM_INCREMENT	1024		/* check in 4 kB increments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define uPD98401_PORTS	0x24		/* probably more ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define uPD98401_OPEN_CHAN	0x20000000 /* open channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define uPD98401_CHAN_ADDR	0x0003fff8 /*	channel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define uPD98401_CHAN_ADDR_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define uPD98401_CLOSE_CHAN	0x24000000 /* close channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define uPD98401_CHAN_RT	0x02000000 /*	RX/TX (0 TX, 1 RX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define uPD98401_DEACT_CHAN	0x28000000 /* deactivate channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define uPD98401_TX_READY	0x30000000 /* TX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define uPD98401_ADD_BAT	0x34000000 /* add batches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define uPD98401_POOL		0x000f0000 /* pool number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define uPD98401_POOL_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define uPD98401_POOL_NUMBAT	0x0000ffff /* number of batches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define uPD98401_NOP		0x3f000000 /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define uPD98401_IND_ACC	0x00000000 /* Indirect Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define uPD98401_IA_RW		0x10000000 /*	Read/Write (0 W, 1 R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define uPD98401_IA_B3		0x08000000 /*	Byte select, 1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define uPD98401_IA_B2		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define uPD98401_IA_B1		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define uPD98401_IA_B0		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define uPD98401_IA_BALL	0x0f000000 /*   whole longword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define uPD98401_IA_TGT		0x000c0000 /*	Target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define uPD98401_IA_TGT_SHIFT	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define uPD98401_IA_TGT_CM	0	   /*	- Control Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define uPD98401_IA_TGT_SAR	1	   /*	- uPD98401 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define uPD98401_IA_TGT_PHY	3	   /*   - PHY device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define uPD98401_IA_ADDR	0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * Command Register Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define uPD98401_BUSY		0x80000000 /* SAR is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define uPD98401_LOCKED		0x40000000 /* SAR is locked by other CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * Indications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Normal (AAL5) Receive Indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define uPD98401_AAL5_UINFO	0xffff0000 /* user-supplied information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define uPD98401_AAL5_UINFO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define uPD98401_AAL5_SIZE	0x0000ffff /* PDU size (in _CELLS_ !!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define uPD98401_AAL5_CHAN	0x7fff0000 /* Channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define uPD98401_AAL5_CHAN_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define uPD98401_AAL5_ERR	0x00008000 /* Error indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define uPD98401_AAL5_CI	0x00004000 /* Congestion Indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define uPD98401_AAL5_CLP	0x00002000 /* CLP (>= 1 cell had CLP=1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define uPD98401_AAL5_ES	0x00000f00 /* Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define uPD98401_AAL5_ES_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define uPD98401_AAL5_ES_NONE	0	   /*	No error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define uPD98401_AAL5_ES_FREE	1	   /*	Receiver free buf underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define uPD98401_AAL5_ES_FIFO	2	   /*	Receiver FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define uPD98401_AAL5_ES_TOOBIG	3	   /*	Maximum length violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define uPD98401_AAL5_ES_CRC	4	   /*	CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define uPD98401_AAL5_ES_ABORT	5	   /*	User abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define uPD98401_AAL5_ES_LENGTH	6	   /*   Length violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define uPD98401_AAL5_ES_T1	7	   /*	T1 error (timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define uPD98401_AAL5_ES_DEACT	8	   /*	Deactivated with DEACT_CHAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define uPD98401_AAL5_POOL	0x0000001f /* Free buffer pool number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* Raw Cell Indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define uPD98401_RAW_UINFO	uPD98401_AAL5_UINFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define uPD98401_RAW_HEC	0x000000ff /* HEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define uPD98401_RAW_CHAN	uPD98401_AAL5_CHAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Transmit Indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define uPD98401_TXI_CONN	0x7fff0000 /* Connection Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define uPD98401_TXI_CONN_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define uPD98401_TXI_ACTIVE	0x00008000 /* Channel remains active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define uPD98401_TXI_PQP	0x00007fff /* Packet Queue Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Directly Addressable Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define uPD98401_GMR	0x00	/* General Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define uPD98401_GSR	0x01	/* General Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define uPD98401_IMR	0x02	/* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define uPD98401_RQU	0x03	/* Receive Queue Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define uPD98401_RQA	0x04	/* Receive Queue Alert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define uPD98401_ADDR	0x05	/* Last Burst Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define uPD98401_VER	0x06	/* Version Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define uPD98401_SWR	0x07	/* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define uPD98401_CMR	0x08	/* Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define uPD98401_CMR_L	0x09	/* Command Register and Lock/Unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define uPD98401_CER	0x0a	/* Command Extension Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define uPD98401_CER_L	0x0b	/* Command Ext Reg and Lock/Unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define uPD98401_MSH(n) (0x10+(n))	/* Mailbox n Start Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define uPD98401_MSL(n) (0x14+(n))	/* Mailbox n Start Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define uPD98401_MBA(n) (0x18+(n))	/* Mailbox n Bottom Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define uPD98401_MTA(n) (0x1c+(n))	/* Mailbox n Tail Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define uPD98401_MWA(n) (0x20+(n))	/* Mailbox n Write Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* GMR is at 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define uPD98401_GMR_ONE	0x80000000 /* Must be set to one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define uPD98401_GMR_SLM	0x40000000 /* Address mode (0 word, 1 byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define uPD98401_GMR_CPE	0x00008000 /* Control Memory Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define uPD98401_GMR_LP		0x00004000 /* Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define uPD98401_GMR_WA		0x00002000 /* Early Bus Write Abort/RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define uPD98401_GMR_RA		0x00001000 /* Early Read Abort/RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define uPD98401_GMR_SZ		0x00000f00 /* Burst Size Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define uPD98401_BURST16	0x00000800 /*	16-word burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define uPD98401_BURST8		0x00000400 /*	 8-word burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define uPD98401_BURST4		0x00000200 /*	 4-word burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define uPD98401_BURST2		0x00000100 /*	 2-word burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define uPD98401_GMR_AD		0x00000080 /* Address (burst resolution) Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define uPD98401_GMR_BO		0x00000040 /* Byte Order (0 little, 1 big) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define uPD98401_GMR_PM		0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define uPD98401_GMR_PC		0x00000010 /* Bus Parity Control (0even,1odd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define uPD98401_GMR_BPE	0x00000008 /* Bus Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define uPD98401_GMR_DR		0x00000004 /* Receive Drop Mode (0drop,1don't)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define uPD98401_GMR_SE		0x00000002 /* Shapers Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define uPD98401_GMR_RE		0x00000001 /* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* GSR is at 0x01, IMR is at 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define uPD98401_INT_PI		0x80000000 /* PHY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define uPD98401_INT_RQA	0x40000000 /* Receive Queue Alert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define uPD98401_INT_RQU	0x20000000 /* Receive Queue Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define uPD98401_INT_RD		0x10000000 /* Receiver Deactivated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define uPD98401_INT_SPE	0x08000000 /* System Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define uPD98401_INT_CPE	0x04000000 /* Control Memory Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define uPD98401_INT_SBE	0x02000000 /* System Bus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define uPD98401_INT_IND	0x01000000 /* Initialization Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define uPD98401_INT_RCR	0x0000ff00 /* Raw Cell Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define uPD98401_INT_RCR_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define uPD98401_INT_MF		0x000000f0 /* Mailbox Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define uPD98401_INT_MF_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define uPD98401_INT_MM		0x0000000f /* Mailbox Modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* VER is at 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define uPD98401_MAJOR		0x0000ff00 /* Major revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define uPD98401_MAJOR_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define uPD98401_MINOR		0x000000ff /* Minor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * Indirectly Addressable Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define uPD98401_IM(n)	(0x40000+(n))	/* Scheduler n I and M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define uPD98401_X(n)	(0x40010+(n))	/* Scheduler n X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define uPD98401_Y(n)	(0x40020+(n))	/* Scheduler n Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define uPD98401_PC(n)	(0x40030+(n))	/* Scheduler n P, C, p and c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define uPD98401_PS(n)	(0x40040+(n))	/* Scheduler n priority and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* IM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define uPD98401_IM_I		0xff000000 /* I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define uPD98401_IM_I_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define uPD98401_IM_M		0x00ffffff /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* PC contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define uPD98401_PC_P		0xff000000 /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define uPD98401_PC_P_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define uPD98401_PC_C		0x00ff0000 /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define uPD98401_PC_C_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define uPD98401_PC_p		0x0000ff00 /* p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define uPD98401_PC_p_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define uPD98401_PC_c		0x000000ff /* c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* PS contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define uPD98401_PS_PRIO	0xf0	/* Priority level (0 high, 15 low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define uPD98401_PS_PRIO_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define uPD98401_PS_S		0x08	/* Scan - must be 0 (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define uPD98401_PS_R		0x04	/* Round Robin (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define uPD98401_PS_A		0x02	/* Active (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define uPD98401_PS_E		0x01	/* Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define uPD98401_TOS	0x40100	/* Top of Stack Control Memory Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define uPD98401_SMA	0x40200	/* Shapers Control Memory Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define uPD98401_PMA	0x40201	/* Receive Pool Control Memory Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define uPD98401_T1R	0x40300	/* T1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define uPD98401_VRR	0x40301	/* VPI/VCI Reduction Register/Recv. Shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define uPD98401_TSR	0x40302	/* Time-Stamp Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* VRR is at 0x40301 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define uPD98401_VRR_SDM	0x80000000 /* Shutdown Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define uPD98401_VRR_SHIFT	0x000f0000 /* VPI/VCI Shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define uPD98401_VRR_SHIFT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define uPD98401_VRR_MASK	0x0000ffff /* VPI/VCI mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * TX packet descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define uPD98401_TXPD_SIZE	16	   /* descriptor size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define uPD98401_TXPD_V		0x80000000 /* Valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define uPD98401_TXPD_DP	0x40000000 /* Descriptor (1) or Pointer (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define uPD98401_TXPD_SM	0x20000000 /* Single (1) or Multiple (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define uPD98401_TXPD_CLPM	0x18000000 /* CLP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define uPD98401_CLPM_0		0	   /*	00 CLP = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define uPD98401_CLPM_1		3	   /*	11 CLP = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define uPD98401_CLPM_LAST	1	   /*	01 CLP unless last cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define uPD98401_TXPD_CLPM_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define uPD98401_TXPD_PTI	0x07000000 /* PTI pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define uPD98401_TXPD_PTI_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define uPD98401_TXPD_GFC	0x00f00000 /* GFC pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define uPD98401_TXPD_GFC_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define uPD98401_TXPD_C10	0x00040000 /* insert CRC-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define uPD98401_TXPD_AAL5	0x00020000 /* AAL5 processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define uPD98401_TXPD_MB	0x00010000 /* TX mailbox number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define uPD98401_TXPD_UU	0x0000ff00 /* CPCS-UU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define uPD98401_TXPD_UU_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define uPD98401_TXPD_CPI	0x000000ff /* CPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * TX buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define uPD98401_TXBD_SIZE	8	   /* descriptor size (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define uPD98401_TXBD_LAST	0x80000000 /* last buffer in packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * TX VC table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* 1st word has the same structure as in a TX packet descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define uPD98401_TXVC_L		0x80000000 /* last buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define uPD98401_TXVC_SHP	0x0f000000 /* shaper number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define uPD98401_TXVC_SHP_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define uPD98401_TXVC_VPI	0x00ff0000 /* VPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define uPD98401_TXVC_VPI_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define uPD98401_TXVC_VCI	0x0000ffff /* VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define uPD98401_TXVC_QRP	6	   /* Queue Read Pointer is in word 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * RX free buffer pools descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define uPD98401_RXFP_ALERT	0x70000000 /* low water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define uPD98401_RXFP_ALERT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define uPD98401_RXFP_BFSZ	0x0f000000 /* buffer size, 64*2^n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define uPD98401_RXFP_BFSZ_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define uPD98401_RXFP_BTSZ	0x00ff0000 /* batch size, n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define uPD98401_RXFP_BTSZ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define uPD98401_RXFP_REMAIN	0x0000ffff /* remaining batches in pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * RX VC table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define uPD98401_RXVC_BTSZ	0xff000000 /* remaining free buffers in batch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define uPD98401_RXVC_BTSZ_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define uPD98401_RXVC_MB	0x00200000 /* RX mailbox number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define uPD98401_RXVC_POOL	0x001f0000 /* free buffer pool number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define uPD98401_RXVC_POOL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define uPD98401_RXVC_UINFO	0x0000ffff /* user-supplied information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define uPD98401_RXVC_T1	0xffff0000 /* T1 timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define uPD98401_RXVC_T1_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define uPD98401_RXVC_PR	0x00008000 /* Packet Reception, 1 if busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define uPD98401_RXVC_DR	0x00004000 /* FIFO Drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define uPD98401_RXVC_OD	0x00001000 /* Drop OAM cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define uPD98401_RXVC_AR	0x00000800 /* AAL5 or raw cell; 1 if AAL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define uPD98401_RXVC_MAXSEG	0x000007ff /* max number of segments per PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define uPD98401_RXVC_REM	0xfffe0000 /* remaining words in curr buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define uPD98401_RXVC_REM_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define uPD98401_RXVC_CLP	0x00010000 /* CLP received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define uPD98401_RXVC_BFA	0x00008000 /* Buffer Assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define uPD98401_RXVC_BTA	0x00004000 /* Batch Assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define uPD98401_RXVC_CI	0x00002000 /* Congestion Indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define uPD98401_RXVC_DD	0x00001000 /* Dropping incoming cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define uPD98401_RXVC_DP	0x00000800 /* like PR ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define uPD98401_RXVC_CURSEG	0x000007ff /* Current Segment count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * RX lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define uPD98401_RXLT_ENBL	0x8000	   /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif